IO-Operations
Symbolic addresses
• The addresses used in a source code. The
variable names, constants, and instruction
labels are the basic elements of the symbolic
address space.
Relative addresses
• At the time of compilation, a compiler
converts symbolic addresses into relative
addresses.
Physical addresses
• The loader generates these addresses at the
time when a program is loaded into main
memory.
Synchronous vs asynchronous I/O
• Synchronous I/O − In this scheme CPU
execution waits while I/O proceeds
• Asynchronous I/O − I/O proceeds
concurrently with CPU execution
Communication to I/O Devices
• The CPU must have a way to pass information
to and from an I/O device. There are three
approaches available to communicate with
the CPU and Device.
• Special Instruction I/O
• Memory-mapped I/O
• Direct memory access (DMA)
Special Instruction I/O
• This uses CPU instructions that
are specifically made for
controlling I/O devices. These
instructions typically allow data
to be sent to an I/O device or
read from an I/O device.
Memory-mapped I/O
• When using memory-mapped I/O, the same address
space is shared by memory and I/O devices.
• The device is connected directly to certain main
memory locations so that I/O device can transfer block
of data to/from memory without going through CPU.
• While using memory mapped IO, OS allocates buffer in
memory and informs I/O device to use that buffer to
send data to the CPU. I/O device operates
asynchronously with CPU, interrupts CPU when
finished.
Direct Memory Access (DMA)
• Slow devices like keyboards will generate an interrupt to the main CPU after
each byte is transferred. If a fast device such as a disk generated an interrupt for
each byte, the operating system would spend most of its time handling these
interrupts. So a typical computer uses direct memory access (DMA) hardware to
reduce this overhead.
• Direct Memory Access (DMA) means CPU grants I/O module authority to read
from or write to memory without involvement. DMA module itself controls
exchange of data between main memory and the I/O device. CPU is only
involved at the beginning and end of the transfer and interrupted only after
entire block has been transferred.
• Direct Memory Access needs a special hardware called DMA controller (DMAC)
that manages the data transfers and arbitrates access to the system bus. The
controllers are programmed with source and destination pointers (where to
read/write the data), counters to track the number of transferred bytes, and
settings, which includes I/O and memory types, interrupts and states for the
CPU cycles.
Kernel I/O Subsystem