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Unit - 3 - Basic Computer Organization and Design

The document describes basic computer organization and design. It discusses computer registers including the data register, address register, accumulator, instruction register, program counter, temporary register, input register, and output register. It also shows the connection of these registers to a common bus and how they are selected using a selection table to read from or write to memory or each other.

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Sudhakar Hallur
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103 views4 pages

Unit - 3 - Basic Computer Organization and Design

The document describes basic computer organization and design. It discusses computer registers including the data register, address register, accumulator, instruction register, program counter, temporary register, input register, and output register. It also shows the connection of these registers to a common bus and how they are selected using a selection table to read from or write to memory or each other.

Uploaded by

Sudhakar Hallur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Unit 3

Basic Computer Organization and Design


Basic Computer Organization and Design
Direct Addressing Mode Indirect Addressing Mode

I=1 I=0
2. Computer Registers
Register Symbol No of Bits Register Name Function
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor Register
IR 16 Instruction Register Holds Instruction Code
PC 12 Program Counter Holds Address of Instruction
TR 16 Temporary Register Holds Temporary Data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds Output character
15 0
15 0 7 0 24
202 24 104 MOV R2, #24H
24 Temporary Register
201 105 ADD R1, R2
200 Input Register
Data Register 15 0 15 0

11 0 104 44
602 202 Instruction Reg Accumulator
601 11 0 7 0
600 105 44
Addr Register
Assume R1 = 20 Program Counter Output Register
Basic Computer Registers Connected to a Common Bus
S2
S1 Bus
Selection Table
Memory Unit
S0
S2 S1 S0 (4096 x 16) Address
7

0 0 0 Write Read
AR 1
LD INR CLR
0 0 1 LD INR CLR

0 1 0 PC
INR CLR
2
LD

0 1 1 DR 3
E
1 0 0 Adder
AC 4
& Logic
1 0 1 LD INR CLR
INPR
1 1 0
IR 5
1 1 1
LD

TR 6
LD INR CLR

OUTR

LD

Clock
16- bit- common bus

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