Vasu DFT
Vasu DFT
Vasu DFT
Manufacturing test
Burn-in
Life-cycles
Board-level integration
Engineering debug
Power
Area
Timing
IDDQ Testing
At Speed Testing
Stuck At Faults
Transistor Faults
Bridging Fault
IDDQ Fault
Transition Fault
Path Delay Fault
FAULT COVERAGE= NUMBER OF DETECTED FAULTS
TOTAL NUMBER OF FAULTS
Detected pattern: 1 0 0 X
15
Vector
1010
1000
1101
0
0
1
PATTERN
BASIC SCAN PATTERN:
A pattern generated by Combinational ATPG, which contains
SCAN LOAD, FORCE ALL PI’S, MEASURE ALL PO’S, SCAN
UNLOAD.
FAST-SEQUENTIAL PATTERN:
A pattern generated by Fast-Sequential ATPG. These patterns
contain from 2 to 10 Clock cycles.
Each clock can contain a scan load, a force of all PI’s and a clock pulse.
The last clock cycle also contains a single measure of PO’s and a Single
Scan Unload
FULL-SEQUENTIAL PATTERN:
These pattern may be generated by Full-Sequential ATPG or
they may come from external source. They contain events that are
incompatible with the Basic Scan and Fast-Sequential Pattern. This can be
simulated only by a Fault Simulator
The main idea of Scan design is to obtain the
Controllability and Observability of Flipflops.
This is done by adding the Test Mode to the
Circuit. When the Circuit is in Test Mode all Flipflops
functionally form one or more Register. These are
called Scan Chain.
TYPES OF SCAN STYLES:
1. MUX Based
2. CLOCK Based
3. LSSD Based
Controllability of circuit
D s@1
0 D 0 0
D1 Q1 D2 Q2 D3
1 1 1 Q3
SI
X
RST
CLK
SE=1
SE=0
To generate the Test Pattern the Comb. ATPG & Seq. ATPG works same.
But in Seq. ATPG, if needs to initialize (Feed) the Flip flops. For this we
need some more patterns.
To generate the patterns in Seq.ATPG first we will convert in to Virtual
Combinational circuit.
In virtual Comb. Circuit it generates the Test Patterns to the Stuck-at-
faults.
This means it removes (assume) the Flip flop and generate the patterns of
that circuit.
This method is called TIME FRAME EXPANSION METHOD.
To generate Test Pattern, there are different type of
ATPG algorithms are used like Exhaust, Podem, Roth’s.
FULL SCAN PARTIAL SCAN
This scan will done for complete circuit This scan will be done for a part of the
circuit
Fault propagate to PO’s and then from Fault propagation till the next nearest flip-
backtracking to PI’s to generate Test flops and backtracks to few PI’s
pattern
Need more vectors to apply all PI’s Need less Vectors
Fault responses output from PO’s Fault response output from Scan out
THEOREM:
A Test pattern that detects all single stuck-at Faults
of the check point of a combinational circuit that
detects all single stuck-at Faults in that circuit.
ASIC FPGA
NRE involves cost for Design, Mask Since Hardware is already available, no
design and hence expensive non recurring expenses (NRE)