8051 Interrupts
8051 Interrupts
µp normal Program
Execution
Normal Program
execution
interrupts.
• XX1, XX2---------XXn address of ISR-2 XX2
ISR in memory. ISR-1 XX1
• When – Interrupt ‘K’ occurs ISR-K for interrupt is
executed by loading address XXK in PC.
• XX1 - ------XXn – starting address of ISR for interrupts.
vector addresses of Interrupts.
Other issues in Interrupts
Hardware/Software Interrupts
Interrupt Priority
Enabling / Disabling of Interrupts.
Masking of Interrupts.
Edge/Level Triggered Hardware Interrupts
• 8051 has five interrupt sources.
• Each interrupt can be programmed to two priority
levels.
INT0 – External Request from P3.2 pin
Timer 0 – Overflow from Timer 0 activates
interrupt request flag TF0.
INT1 – External Request from P3.3
Timer1- Overflow from Timer1 activates
interrupt request flag TF1
Serial Port – completion of transmission or
reception of a serial frame activates the flags TI
or RI.
• The complete interrupt system may be disabled or
enabled by storing 0 or 1 in EA bit of IE SFR
- IE.7.
SETB IE.7, - Enable Interrupts
CLR IE.7, - Disable Interrupts
• When Interrupt system is enabled i.e. IE.7=1, then
each of the five interrupts can be enabled/disabled
individually by making a specified bit in IE register as
1 or 0.
- Interrupt masking
bit = 0 – Interrupt is disabled i.e. masked
bit = 1 – Interrupt is enabled
IE Register – Interrupt Enable Register
7 6 5 4 3 2 1 0
EA X X ES ET1 EX1 ET0 EX0
=50H
MOV SCON, #50H
; Enable Serial Interrupt.
7 6 5 4 3 2 1 0
IE = EA X X ES ET1 EX1 ET0 EX0
1 0 0 1 0 0 0 0
= 90H
MOV IE, # 90H
; Set Priority as High
7 6 5 4 3 2 1 0
X X X PS PT1 Px1 PT0 PX0
IP =
0 0 0 1 0 0 0 0
=10H
MOV IP, # 10H
; Set Timer 1 to mode 2 Auto read
TMOD = Timer 1 Timer 0
Gate C/T M1 M0
0 0 1 0