Verilog HDL - Introduction

Verilog HDL -Introduction
Typical Design Flow (in 1996)

1. Design specification
2. Behavioral description
3. RTL description
4. Functional verification and testing
5. Logic synthesis
6. Gate-level netlist
7. Logical verification and testing
8. Floor planning, automatic place & route
9. Physical layout
Basics of Digital Design Using
HDLs
Stimulus block
Generating Checking
inputs Circuit Under Design outputs
to CUD (CUD) of CUD
4
8
Test bench
Simulation- Test Bench Styles
Design Methodologies
4-bit Ripple Carry Counter
T-flipflop and the Hierarchy
Ports
 Ports provide interface for by which a module can
communicate with its environment
Port connection rules
Connecting Ports
 Suppose we have a module
Module- Basic building block
A module can be an element or collection of low level design

blocks
Module
Modules (cont’d)
 Verilog supported levels of abstraction
 Behavioral (algorithmic) level
 Describe the algorithm used
 Very similar to C programming
14
 Dataflow level
 Describe how data flows between registers and is processed
 Gate levelInterconnect logic gates
 Switch level
 Interconnect transistors (MOS transistors)
 Register-Transfer Level (RTL)

 Generally known as a combination of behavioral+dataflow that
Instance
 A module provides a template which you
can create actual objects.
 When a module is invoked, Verilog
creates a unique object from the template
 The process of creating a object from
module template is called instantiation
 The object is called instance
Instances
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module TFF are created.
TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);

Instances (cont’d)
module TFF(q, clk, reset);
output q;
input clk, reset;
wire d;
DFF dff0(q, d, clk, reset);
not n1(d, q); // not is a Verilog provided primitive.
endmodule
// module DFF with asynchronous reset
module DFF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
always @(posedge reset or negedge clk)

if (reset)
q = 1'b0;
else
q = d;
endmodule
How to build and test a module
Construct a “test bench” for your design

– Develop your hierarchical system within a module that has
input and output ports (called “design” here)
– Develop a separate module to generate tests for the module
(“test”)
– Connect these together within another module (“testbench”)
module testbench (); module design (a, b, c);
wire l, m, n; input a, b;
output c;
design d (l, m, n); …
test t (l, m);
initial begin
//monitor and display
module test (q, r);
…
output q, r;
initial begin
//drive the outputs with signals
…
Another view of this
• 3 chunks of verilog, one for each of:
TESTBENCH is the final piece of hardware which

connect DESIGN with TEST so the inputs generated
go to the design you want to test...
Another piece of
hardware, called Your hardware
TEST, to generate called
interesting inputs DESIGN
Verilog Examples
Module testAdd generated inputs for module halfAdd and
displayed changes. Module halfAdd was the design
module testAdd(a, b, sum, cOut);
module tBench;
input sum, cOut;
wire su, co, a, b;
output a, b;
reg a, b;
halfAdd ad(su, co, a, b);
testAdd tb(a, b, su, co);
initial begin
endmodule
$monitor ($time,,
“a=%b, b=%b, sum=%b, cOut=%b”,
a, b, sum, cOut);
module halfAdd (sum, cOut, a, b); a = 0; b = 0;
output sum, cOut; #10 b = 1;
input a, b; #10 a = 1;
#10 b = 0;
xor #2 (sum, a, b); #10 $finish;
and #2 (cOut, a, b); end
endmodule endmodule
Gate Level Modeling
 A logic circuit can be designed by use of logic
gates.
 Verilog supports basic logic gates as predefined
primitives. These primitives are instantiated like
modules except that they are predefined in Verilog
and do not need a module definition.
Gate gate_name(out,in1,in2…)
Buf/not gates
 Buflnot gates have one scalar input and
one or more scalar outputs.
Bufif/notif
Instantiation of bufif gates
Design of 4:1 Multiplexer
Contd..
Stimulus
4 bit full adder
Declaration:
Code contd..
4 bit adder using 1 bit adder
Stimulus
Gate Delays:
 Rise Delay: Delay associated with a
o/p transition to 1 from any value.
Fall Delay: Delay associated with o/p

transition to 0 from any value.
Turn off Delay: Delay associate with
o/p transition to Z from another
value.
Min value
The min vale is the minimum delay value that the designer expects the
gate to have.
Type value
The type value is the typical delay value that the designer expects the gate
to have.
Max value
The max value is the maximum delay value that the designer expects the
gate to have.
//min delay=4
//type delay=5
//max delay=6
and #(4:5:6) a1(out, i1, i2) ;
//min delay, rise=3 , fall =5

//type delay, rise=4 , fall =6
//max delay, rise=5 , fall =7
and #(3:4:5, 5:6:7) a2(out, i1, i2 ) ;
//min delay, rise=2 , fall =3 , turn-off =4

//type delay, rise=3 , fall =4 , trun-off=5
//max delay, rise=4 , fall =5 , trun-off=6
and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1, i2 ) ;

Dataflow Modeling
 In complex designs the number of gates
is very large
 Currently, automated tools are used to

create a gate-level circuit from a
dataflow design description. This
process is called logic synthesis
Continuous Assignment
Rules:
 The left hand side of an assignment must always
be a scalar or vector net
 It cannot be a scalar or vector register.
 Continuous assignments are always active.
 The assignment expression is evaluated as soon

as one of the right-hand-side operands changes
and the value is assigned to the left-hand-side
net.
 The operands on the right-hand side can
be registers or nets.
 Delay values can be specified for

assignments in terms of time units. Delay
values are used to control the time when
a net is assigned the evaluated value
• Implicit Continious Assignment
//Regular Continious Assignment

wire= out;
assign out = in1& in2;
//same effect is achieved by an implicit assignment
Wire out = in1& in2;
• Implicit Net Declaration
//Continious Assignment,out is a net

Wire i1, i2;
assign out = in1& in2;
Delay
Implicit Continuous Assignment Delay
wire #10 out = in1 & in2;
Net Declaration Delay

wire #10 out ;
assign out = in1 & in2;
Operator Types
Conditional Operator
4:1 Multiplexer Example
User Defined Primitives (UDPs)
• Keywords and, or, not, xor, etc. are System

Primitives
• Can Define your Own Primitives (UDPs)
• Can do this in a variety of ways including Truth
Tables
• Instead of module/endmodule use the keywords
primitive/endprimitive
• Only one output and must be listed first
• Keywords table and endtable used
• Input values listed in order
• Output is always last entry
HDL Example 2
//User defined primitive(UDP)

primitive crctp (x,A,B,C); // user defined
output x;
input A,B,C;
//Truth table for x(A,B,C) = Minterms ( ? )
table // truth table
// A B C : x (Note that this is only a comment)
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive
Primitives
• Pre-defined primitives
– Total 26 pre-defined primitives
– All combinational
– Tri-state primitives have multiple output, others have single
output
• User-Defined Primitives (UDP)

– Combinational or sequential
– Single output
• UDP vs. modules

– Used to model cell library
Shorthand Notation
primitive mux_prim ( out, select, a, b );
output out;
input select, a, b;
table
//select a b : out
0 0 ? : 0; // ? => iteration of table entry over 0, 1, x.

select
0 1 ? : 1; a
// i.e., don’t care on the input
mux_prim
1 ? 0 : 0; b out
1 ? 1 : 1;
? 0 0 : 0;
UDP: Sequential Behavior
• In table description, n+2 columns for n
input
• n input columns + internal state column
+ output (next state) column
• Output port -> reg variable
Level-sensitive Behavior
primitive transparent_latch(out, enable, in);
enable
output out;
in Transparent out
input enable, in;
latch
reg out;
table
//enable in state out/next_state
1 1 :? : 1;
1 0 :? : 0;
0 ? :? : -; // ‘-’ -> no change
x 0 :0 : -;
Edge-sensitive Behavior
primitive d_flop( q, clock, d );
clock
output q;
d d_flop q
input clock, d;
reg q;
table
// clock d state q/next_state
(01) 0 : ? : 0; // Parentheses indicate signal transition
(01) 1 : ? : 1; // Rising clock edge
(0?) 1 : 1 : 1;
(0?) 0 : 0 : 0;
(?0) ? : ? : -; // Falling clock edge

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Verilog HDL -Introduction

Typical Design Flow (in 1996)

A module can be an element or collection of low level design

 Register-Transfer Level (RTL)

input clk, reset;

//4 instances of the module TFF are created.

TFF tff0(q[0],clk, reset);

TFF tff1(q[1],q[0], reset);

TFF tff2(q[2],q[1], reset);

TFF tff3(q[3],q[2], reset);

always @(posedge reset or negedge clk)

Construct a “test bench” for your design

TESTBENCH is the final piece of hardware which

Fall Delay: Delay associated with o/p

//min delay, rise=3 , fall =5

//min delay, rise=2 , fall =3 , turn-off =4

and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1, i2 ) ;

 Currently, automated tools are used to

 It cannot be a scalar or vector register.

 Continuous assignments are always active.

 The assignment expression is evaluated as soon

 Delay values can be specified for

//Regular Continious Assignment

//Continious Assignment,out is a net

Net Declaration Delay

• Keywords and, or, not, xor, etc. are System

//User defined primitive(UDP)

• User-Defined Primitives (UDP)

• UDP vs. modules

0 0 ? : 0; // ? => iteration of table entry over 0, 1, x.

//enable in state out/next_state

0 ? :? : -; // ‘-’ -> no change

// clock d state q/next_state

(01) 0 : ? : 0; // Parentheses indicate signal transition

(01) 1 : ? : 1; // Rising clock edge

(?0) ? : ? : -; // Falling clock edge

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