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Subsystem Design: FPGA Based Systems

The document discusses various topics related to VLSI system design including subsystem design, architectural issues, switch logic, gate logic, parity generators, multiplexers, programmable logic arrays, and FPGA-based systems. Some key guidelines for designing VLSI systems include properly defining requirements, partitioning into subsystems, considering communication paths, drawing a floor plan, aiming for regular structures, and simulating performance. Switch logic uses pass transistors to reduce transistor counts while gate logic uses inverters, NAND gates, and NOR gates. Parity generators are used to add a parity bit to ensure an even or odd number of ones. PLDs like PLA can be programmed to implement custom logic functions using an input connection matrix and

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86 views38 pages

Subsystem Design: FPGA Based Systems

The document discusses various topics related to VLSI system design including subsystem design, architectural issues, switch logic, gate logic, parity generators, multiplexers, programmable logic arrays, and FPGA-based systems. Some key guidelines for designing VLSI systems include properly defining requirements, partitioning into subsystems, considering communication paths, drawing a floor plan, aiming for regular structures, and simulating performance. Switch logic uses pass transistors to reduce transistor counts while gate logic uses inverters, NAND gates, and NOR gates. Parity generators are used to add a parity bit to ensure an even or odd number of ones. PLDs like PLA can be programmed to implement custom logic functions using an input connection matrix and

Uploaded by

Lohith c
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 4:

• Subsystem Design
• Some Architectural Issues
• Switch Logic
• Gate(restoring) Logic
• Parity Generators
• Multiplexers
• The Programmable Logic Array (PLA)
• FPGA Based Systems:
• Introduction, Basic concepts, Digital design and
FPGA’s, FPGA based System design, FPGA architecture,
Physical design for
FPGA’s
Some Architectural Issues
• In all design processes, a logical and systematic
approach is essential. This is particularly so in the case
of the design of a VLSI system which could otherwise
take so long as to render the whole system obsolete
before it is off the drawing board.

• MSI logic circuit comprising, say, 500 transistors - two


engineermonths

• 500,000 transistor VLSI system - How many


engineering months ?
Guidelines for designing VLSI systems
1. Define the requirements (properly and carefully)
2. Partition the overall architecture into appropriate subsystems.
3. Consider communication paths carefully in order to develop sensible
interrelationships
between subsystems.
4. Draw a floor plan of how the system is to map onto the silicon (and
alternate
between 2, 3 and 4 as necessary).
5. Aim for regular structures so that design is largely a matter of
replication.
6. Draw suitable (stick or symbolic) diagrams of the leaf-cells of the
subsystems.
7. Convert each cell to a layout.
8. Carefully and thoroughly carry out 'a design rule check on each cell.
9. Simulate the performance of each cell/subsystem.
A floorplanning is the process of placing blocks/macros in the chip/core area,
thereby determining the routing areas between them.
Partitioning is a process of dividing the chip into small blocks. This is done mainly to
separate different functional blocks and also to make placement and routing easier.
Designing Digital Systems
• In designing digital systems in MOS
technology there are two basic ways of
building logic circuits, which will now be
discussed.
• SWITCH LOGIC
• GATE (restoring) LOGIC
SWITCH LOGIC
• Switch logic is based on pass transistors or
transmission gates. Pass transistor describes
several logic families used in the design of
integrated circuits.
• This logic reduces the count of transistors
used to make different logic gates, by
eliminating redundant transistors.
• The whole design process will be greatly assisted if
considerable care is taken with:
1. The partitioning of the system so that there are clean and
clear subsystems with a minimum interdependence and
complexity of interconnection between them.
2. The design simplification within subsystems so that
architectures are adopted which allow the exploitation of
a cellular design concept. This allows the system to be
composed of relatively few standard cells which are
replicated to form highly regular structures.
Pass Transistors and Transmission Gates
GATE (restoring) LOGIC
• The Inverter
• Two-Input nMOS, CMOS and BICMOS NAND Gates
• Two-Input nMOS, CMOS and BICMOS NOR Gates
Other Forms of CMOS Logic
• Pseudo-nMOS logic
• Dynamic CMOS logic
• Clocked CMOS (C2MOS) logic
• CMOS domino logic
• n-p CMOS logic
Pseudo-nMOS logic
Dynamic CMOS logic
Clocked CMOS (C2MOS) logic
CMOS domino logic
n-p CMOS logic
A Parity Generator
• Parity checking is a method in which an extra
bit called parity bit is appended, usually at the
MSB, of the data stream which needs to be
transmitted. Now, how to decide whether to
add 1 or 0? This depends on whether we
desire to have odd parity or even parity.
Odd Parity
• This is the case wherein the number of ones in
the bit stream sent (data bits in conjunction with
parity-bit) has to be maintained as an odd
number. That is, suppose we have our bit stream
as 1001011, then the parity would be generated
as 1 such that the number of ones in the resulting
bit-stream (= 11001011) is 5, an odd number.
Reasoning in similar fashion, we can say that for
the data sequence of 1001010, the parity-bit
should necessarily be 0
Even Parity
• In case if we opt for even parity, then we need
to ensure that the total number of ones in the
bit stream, including the parity bit, becomes
an even number. For example, if the data
string is 1001011, then the parity-bit would be
0; while if it is 1001010, then parity-bit should
be 1.
Multiplexers (Data Selectors)
PLD
• The purpose of a PLD device is to permit elaborate digital logic
designs to be implemented by the user in a single device.

• Can be erased electrically and reprogrammed with a new design,


making them very well suited for academic and prototyping

• Types of Programmable Logic Devices


• SPLDs (Simple Programmable Logic Devices)
– ROM (Read-Only Memory)
– PLA (Programmable Logic Array)
– PAL (Programmable Array Logic)
– GAL (Generic Array Logic)
• CPLD (Complex Programmable Logic Device)
• FPGA (Field-Programmable Gate Array)

29
General structure of PLDs.

30
PLD
• The first three varieties(ROM, PLA, PAL) are quite
similar to each other:
– They all have an input connection matrix, which connects
the inputs of the device to an array of AND-gates.
– They all have an output connection matrix, which connect
the outputs of the AND-gates to the inputs of OR-gates
which drive the outputs of the device.

• The gate array is significantly different and will be


described later.

31
PLA

32
PLA

• A 3×2 PLA with 4 product terms.


33
JK FF implementation using PLA

34
Design for PLA:
Example
– Implement the following functions using PLA
F0 = A + B' C'
F1 = A C' + A B Input Side:
F2 = B' C' + A B
F3 = B' C + A 1 = asserted in term
0 = negated in term
- = does not participate
Personality Matrix
Product Inputs Outputs
term A B C F0 F1 F2 F3 Output Side:
AB 1 1 - 0 1 1 0 1 = term connected to output
Reuse 0 = no connection to output
BC - 0 1 0 0 0 1
AC 1 - 0 0 1 0 0 of
terms
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1

35
Example: Continued
A B C

F0 = A + B' C' AB
F1 = A C' + A B
F2 = B' C' + A B B’C
F3 = B' C + A
AC’
B’C’

Personality Matrix A

Produc t Inputs Outputs


term A B C F0 F1 F2 F3
AB 1 1 - 0 1 1 0 F0 F1 F2 F3
BC - 0 1 0 0 0 1 Reus e
AC 1 - 0 0 1 0 0 of
1 0 1 0 terms
BC - 0 0
A 1 - - 1 0 0 1

36

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