What is Verilog

• Hardware Description Language (HDL)

• Developed in 1984

• Standard: IEEE 1364, Dec 1995

Basic Limitation of Verilog

Description of digital systems only

Main Language Concepts (i)

• Concurrency

• Structure
 Main Language Concepts (ii)

• Procedural Statements

• Time
 User Identifiers
• Formed from {[A-Z], [a-z], [0-9], _, $}, but ..
• .. can’t begin with $ or [0-9]
– myidentifier
– m_y_identifier
– 3my_identifier
– $my_identifier
– _myidentifier$

• Case sensitive
– myid  Myid
 Comments

• // The rest of the line is a comment

• /* Multiple line
comment */

• /* Nesting /* comments */ do NOT work */

 Verilog Value Set
• 0 represents low logic level or false condition

• 1 represents high logic level or true condition

• x represents unknown logic level

• z represents high impedance logic level

 Numbers in Verilog (i)
<size>’<radix> <value>

No
Noofof Binary
Binary bbor
orBB Consecutive
Consecutivechars
chars
bits
bits Octal
Octal ooor
orOO 0-f,
0-f,x,x,zz
Decimal 
Decimal ddor
orDD
Hexadecimal
Hexadecimal hhororHH

– 8’h ax = 1010xxxx
– 12’o 3zx7 = 011zzzxxx111
 Numbers in Verilog (ii)
• You can insert “_” for readability
– 12’b 000_111_010_100
– 12’b 000111010100 Represent the same number
– 12’o 07_24
• Bit extension
– MS bit = 0, x or z  extend this
• 4’b x1 = 4’b xx_x1
– MS bit = 1  zero extension
• 4’b 1x = 4’b 00_1x
 Numbers in Verilog (iii)
• If size is ommitted it
– is inferred from the value or
– takes the simulation specific number of bits or
– takes the machine specific number of bits

• If radix is ommitted too .. decimal is assumed

– 15 = <size>’d 15
 Nets (i)
• Can be thought as hardware wires driven by
logic
• Equal z when unconnected
• Various types of nets
– wire
– wand (wired-AND)
– wor (wired-OR)
– tri (tri-state)
 Nets (ii)

In this example: Y is evaluated, automatically,

every time A or B changes

A wire Y; // declaration
Y
B assign Y = A & B;
 Registers
• Variables that store values
• Do not represent real hardware but ..
• .. real hardware can be implemented with registers
• Only one type: reg
reg A, C; // declaration
// assignments are always done inside a procedure
A = 1;
C = A; // C gets the logical value 1
A = 0; // C is still 1
C = 0; // C is now 0

• Register values are updated explicitly!!

 Vectors
• Represent buses
wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;

• Left number is MS bit

• Slice management
busC[1] = busA[2];
busC = busA[2:1]; 
busC[0] = busA[1];

• Vector assignment (by position!!)

busB[1] = busA[3];
busB[2] = busA[2];
busB = busA;
busB[3] 
= busA[1];
busB[4] = busA[0];
 Integer & Real Data Types
• Declaration
integer i, k;
real r;

• Use as registers (inside procedures)

i = 1; // assignments occur inside procedure
r = 2.9;
k = r; // k is rounded to 3

• Integers are not initialized!!

• Reals are initialized to 0.0
 Time Data Type
• Special data type for simulation time measuring
• Declaration
time my_time;

• Use inside procedure

my_time = $time; // get current sim time

• Simulation runs at simulation time, not real time

 Arrays (ii)
• Limitation: Cannot access array subfield or
entire array at once
var[2:9] = ???; // WRONG!!
var = ???; // WRONG!!

• No multi-dimentional arrays
reg var[1:10] [1:100]; // WRONG!!

• Arrays don’t work for the Real data type

real r[1:10]; // WRONG !!
 Strings
• Implemented with regs:
reg [8*13:1] string_val; // can hold up to 13 chars
..
string_val = “Hello Verilog”;
string_val = “hello”; // MS Bytes are filled with 0
string_val = “I am overflowed”; // “I ” is truncated

• Escaped chars:
– \n newline
– \t tab
– %% %
– \\ \
– \“ “
 Hierarchical Design

Top
TopLevel
Level E.g.
Module
Module

Full
FullAdder
Adder
Sub-Module
Sub-Module Sub-Module
Sub-Module
11 22

Half
HalfAdder
Adder Half
HalfAdder
Adder
Basic
BasicModule
Module Basic
BasicModule
Module Basic
BasicModule
Module
11 22 33
 Module
module my_module(out1, .., inN);
in1 my_module out1 output out1, .., outM;
in2 out2 input in1, .., inN;

f .. // declarations
inN outM .. // description of f (maybe
.. // sequential)

endmodule

Everything you write in Verilog must be inside a module

exception: compiler directives
 Example: Half Adder

A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;

A S assign S = A ^ B;
Half assign C = A & B;
Half
B Adder
Adder C
endmodule
 Example: Full Adder
in1 A S I1 A S sum
Half
Half Half
Half
Adder
Adder11 I2 Adder
Adder
in2 B C B C I3
ha1
ha1 ha2
ha2 cout

cin
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;

wire sum, cout, in1, in2, cin;

Module wire I1, I2, I3; Instance
name name
half_adder ha1(I1, I2, in1, in2);
half_adder ha2(sum, I3, I1, cin);

assign cout = I2 || I3;

endmodule