Introduction to Microprocessors

&
8086 Architecture
BY
P. PRASANTH KUMAR
ASSISTANT PROFESSOR
EEE DEPARTMENT
GRIET
 Contents
 Introduction to Microprocessor

 8086 Architecture: Functional Diagram

 Register Organization

 Memory Segmentation

 Programming Model

 Memory Address

 Physical Memory Organization

 Signal Description of 8086

 Timing Diagrams

 Interrupts of 8086
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S.No Course Outcomes

Compare the functionally and architectures of microprocessors and

1
microcontrollers

2 Analyze assembly language programming techniques

3 Explain the implementation of 8051 instruction set

4 Analyze assembly language programming concepts

5 Acquainted with design of microcontrollers

6 Interface various devices with microcontrollers

7 Design various programs to run several applications

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 Definition of the Microprocessor
The microprocessor is a programmable device
that takes in numbers, performs on them
arithmetic or logical operations according to the
program stored in memory and then produces
other numbers as a result.

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Lets expand each of the underlined words:
Programmable device:
• The microprocessor can perform different sets of operations on
the data it receives depending on the sequence of instructions
supplied in the given program.

• By changing the program, the microprocessor manipulates the

data in different ways.
Instructions:
• Each microprocessor is designed to execute a specific group of
operations. This group of operations is called an instruction set.
This instruction set defines what the microprocessor can and
cannot do.
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Takes in:

The data that the microprocessor manipulates

must come from somewhere.
– It comes from what is called “input devices”.

– These are devices that bring data into the system

from the outside world.

– These represent devices such as a keyboard, a

mouse, switches, and the like.

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Numbers:
The microprocessor has a very narrow view on life. It
only understands binary numbers.

• A binary digit is called a bit (which comes from binary

digit).

• The microprocessor recognizes and processes a group

of bits together. This group of bits is called a “word”.

• The number of bits in a Microprocessor’s word, is a

measure of its “abilities”.

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 Features of 8086 Microprocessor
It is a 16-bit μp.
8086 has a 20 bit address bus can access up to 220
memory locations (1 MB).

Address ranges from 00000H to FFFFFH.

 It can support up to 64K I/O ports.
 It provides Fourteen, 16 -bit registers.
It has multiplexed address and data bus i.e. AD0-
AD15 and A16 – A19.
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 8086 is designed to operate in two modes, Minimum
and Maximum.

 It can prefetches up to 6 instruction bytes from

memory and queues them in order to speed up
instruction execution.

 It requires +5V power supply.

 A 40 pin dual in line package.

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Internal Architecture of 8086

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 Architecture of 8086
The 8086 CPU logic has been partitioned into two
functional units namely

 Bus Interface Unit (BIU)

 Execution Unit (EU).
The major reason for this separation is to increase the
processing speed of the processor.

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 The BIU sends out addresses, fetches instructions from memory,
reads data from ports and memory, and writes data to ports and
memory.

 In other words, the BIU handles all transfers of data and

addresses on the buses for the execution unit.

 Execution Unit (EU) tells the BIU where to fetch instructions or

data from, decodes instructions, and execute instructions.

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• The Execution Unit (EU) has
¥ Control unit

¥ Instruction decoder

¥ Arithmetic and Logical Unit (ALU)

¥ General registers

¥ Pointers

¥ Index registers

¥ Flag register

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 Execution Unit (EU)
• Control unit is responsible for the co-ordination of all
other units of the processor

• ALU performs various arithmetic and logical

operations over the data

• The Instruction Decoder translates the instructions

fetched from the memory into a series of actions that
are carried out by the EU

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 Execution Unit - Registers
• General registers are used for temporary storage and
manipulation of data and instructions.

• Accumulator register consists of two 8-bit registers AL and AH,

which can be combined together and used as a 16-bit register AX

• Accumulator can be used for I/O operations and string

manipulation.

• Base register consists of two 8-bit registers BL and BH, which can
be combined together and used as a 16-bit register BX

• BX register usually contains a data pointer used for based, based

indexed or register indirect addressing.
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• Count register consists of two 8-bit registers CL and CH, which can
be combined together and used as a 16-bit register CX

• Count register can be used as a counter in string manipulation and

shift/rotate instructions.

• Data register consists of two 8-bit registers DL and DH, which can
be combined together and used as a 16-bit register DX

• Data register can be used to hold 16 bit result in 16 in 16x16

multiplication.

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Pointers:
To get 20-bit physical address one or more pointer (SP and BP) or
index registers ( SI and DI) are associated with each segment
register.

Stack pointer (SP) and Base Pointer (BP) are used to access data in
the stack segment.

Stack Pointer:
• Stack Pointer (SP) is a 16-bit register pointing to program stack.

• SP is used as an offset from the current SS during execution of

instructions that involve the stack segment in external memory.

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Base Pointer (BP):
Base Pointer (BP) is a 16-bit register pointing to data in stack
segment. BP register is usually used for based, based indexed or
register indirect addressing.

BP is used in based addressing mode.

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 Index Registers:
Source Index Register (SI) and Destination Index Registers (DI) are
used in indexed addressing.

• Source Index (SI) is a 16-bit register. SI is used for indexed,

based indexed and register indirect addressing, as well as a
source data addresses in string manipulation instructions.

• Destination Index (DI) is a 16-bit register. DI is used for

indexed, based indexed and register indirect addressing, as well
as a destination data addresses in string manipulation
instructions.

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 Flag Register
Auxiliary Carry Flag Carry Flag
Sign Flag
This is set, if there is a carry from the lowest nibble, This flag is set, when there is a
This flag is set, when the result
i.e, bit three during addition, or borrow for the lowest carry out of MSB in case of addition
of any computation is negative
nibble, i.e, bit three, during subtraction. or a borrow in case of subtraction.

Trap Flag Parity Flag

If this flag is set, the processor Zero Flag
enters the single step execution This flag is set to 1, if the lower byte of
mode by generating internal This flag is set, if the result of the
computation or comparison the result contains even number of
interrupts after the execution of each 1’s ; for odd number of 1’s set to zero.
instruction performed by an instruction is zero

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Interrupt Flag

Causes the 8086 to recognize external

Over flow Flag mask interrupts; clearing IF disables these
This flag is set, if an overflow occurs, i.e, if the result of a signed interrupts.
operation is large enough to accommodate in a destination
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit Direction Flag
sign operations, then the overflow will be set. This is used by string manipulation instructions. If this flag bit is ‘0’, the
string is processed beginning from the lowest address to the highest
address, i.e., auto incrementing mode. Otherwise, the string is
processed from the highest address towards the lowest address, i.e.,
auto decrementing mode.
Execution Unit - Flag

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 Bus Interface Unit (BIU)
Contains
• 6-byte Instruction Queue (Q)
• The Segment Registers (CS, DS, ES, SS).
• The Instruction Pointer (IP).
• The Address Summing block (Σ)

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 Queue (Q)
• To speed up program execution, the BIU fetches a six instruction
bytes ahead of time from the memory.

• These prefetched instruction bytes are held for the EU in a group

of registers called QUEUE.

• With the help of QUEUE it is possible to fetch next instruction

when current instruction is in execution.

• The QUEUE operates on the principle First-in-First out (FIFO).

• Feature of fetching next instruction while the current instruction

is executing is called PIPELINING.

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 Segment Registers
• In 8086/88 the processors have 4 segments registers
– Code Segment register (CS)
– Data Segment register (DS)
– Extra Segment register (ES)
– Stack Segment (SS) register.

• All are 16-bit registers.

• Each of the Segment registers store the upper 16 bit

address of the starting address of the corresponding
segments.

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 Segment Registers
• Code Segment (CS) register is a 16-bit register containing
address of 64 KB segment with processor instructions

• The processor uses CS segment for all accesses to

instructions referenced by instruction pointer (IP) register

• Stack Segment (SS) register is a 16-bit register containing

address of 64KB segment with program stack

• By default, the processor assumes that all data referenced by

the stack pointer (SP) and base pointer (BP) registers is
located in the stack segment
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• Data Segment (DS) register is a 16-bit register containing
address of 64KB segment with program data

• By default, the processor assumes that all data referenced by

general registers (AX, BX, CX, DX) and index register (SI,
DI) is located in the data segment

• Extra Segment (ES) register is a 16-bit register containing

address of 64KB segment, usually with program data

• By default, the processor assumes that the DI register

references the ES segment in string manipulation instructions

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 Physical Memory Organization
 The 8086 processor provides a 20-bit address to access
any location of the 1 MB memory space.
 The memory is organized as a linear array of 1 million
bytes, addressed as 00000(H) to FFFFF(H).
 Physically, the memory is organized as a high bank
(D15 - D8) and a low bank (D7 –D0) of 512 K 8-bitbytes
addressed in parallel by the processor's address lines A19 -
A1.

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 Physical Memory Organization
 Byte data with even addresses is transferred on the D7 – D0
bus lines while odd addressed byte data (A0 HIGH) is
transferred on the D15-D8 bus lines.
 The processor provides two enable signals, BHE and A0, to
selectively allow reading from or writing into either an odd byte
location, even byte location, or both.
BHE A0 TYPE OF DATA TRANSFER AND BANK SELECTION

0 0 16-bit data transfer, both banks selected

0 1 8-bit data transfer, Odd bank selected
1 0 8-bit data transfer, Even bank selected
1 1 No Data Transfer, both banks disabled.

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 Segmentation
 Segmentation is the process in which the main memory
of computer is divided into different segments and each
segment has its own base address.

 Segmentation is used to increase the execution speed of

computer system so that processor can able to fetch and
execute the data from memory easily and fastly.

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 Types of Segmentation
Overlapping Segment:
 A segment starts at a particular address and its maximum
size can go up to 64 Kbytes. But if another segment starts
along this 64 Kbytes location of the first segment, the two
segments are said to be overlapping segment.
 The area of memory from the start of the second segment
to the possible end of the first segment is called as
overlapped segment.
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Non-Overlapped Segment:
 A segment starts at a particular address and its maximum
size can go up to 64 Kbytes. But if another segment starts
before this 64 Kbytes location of the first segment, the two
segments are said to be Non- overlapping segment.

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Memory Segmentation Physical Memory

00000
The memory in an 8086/88 based
system is organized as segmented
Code segment (64KB)
memory.
The CPU 8086 is able to address

1 MB
Data segment (64KB)

1Mbyte of memory.
Extra segment (64KB)
The Complete physically available
Stack segment (64KB)
memory may be divided into a
number of logical segments.
FFFFF

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• The size of each segment is 64 KB

• A segment may be located any where in the memory

• The 4 segments are Code, Data, Extra and Stack segments.

• The 16-bit contents of the segment registers in the BIU actually

point to the starting location of a particular segment.

• Segments may be overlapped or non-overlapped

• Each of these segments can be used for a specific function.

– Code segment is used for storing the instructions.
– The stack segment is used as a stack and it is used to store the
return addresses.
– The data and extra segments are used for storing data byte.
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 Generating a Physical Address
The 8086 addresses a segmented memory.
The complete physical address which is 20-bits long is generated
using segment and offset registers, each 16-bit long.
 The content of segment register (segment address) is shifted
left bit-wise four times.
 The content of an offset register (offset address) is added to
the result of the previous shift operation.
These two operations together produce a 20-bit physical address.

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• The following examples shows the CS:IP scheme of
address formation:

CS 34BA IP 8AB4 Code segment

34BA0
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR 8AB4 (offset)
four binary digits left
3D654

34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F
Segment and Address register combination

• CS:IP

• SS:SP SS:BP

• DS:BX DS:SI DS:DI

• ES:DI (for string operations)

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Pin Diagram of 8086
Common signals AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5,

A19/S6
High order address bus. These are
multiplexed with status signals
Common signals BHE (Active Low)/S7 (Output)
Bus High Enable/Status
It is used to enable data onto the most significant
half of data bus, D8-D15.
8-bit device connected to upper half of the data bus
use BHE (Active Low) signal.
It is multiplexed with status signal S7.

MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.
It is an output signal.
It is active when low.
Common signals
TEST
TEST input is tested by the WAIT
instruction.
8086 will enter a wait state after execution
of the WAIT instruction and will resume
execution only when the TEST is made low
by an active hardware.
This is used to synchronize an external
activity to the processor internal operation.

READY
This is the acknowledgement from the
slow device or memory that they have
completed the data transfer.
The signal made available by the devices
is synchronized by the 8284A clock
generator to provide ready input to the
8086.
The signal is active high.
Common signals
RESET (Input)
Causes the processor to immediately terminate
its present activity.
The signal must be active HIGH for at least four
clock cycles.

GND (Output)
GROUND

CLK
The clock input provides the basic timing
for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.
Common signals INTR Interrupt Request
This is a triggered input. This is sampled during
the last clock cycles of each instruction to
determine the availability of the request.
If any interrupt request is pending, the processor
enters the interrupt acknowledge cycle.
This signal is active high and internally
synchronized.

NMI (Non-Maskable
Interrupt)
It is an edge triggered input which causes a
type 2 interrupt.
NMI is not maskable internally by software.

Vcc
Power Supply (+5V DC)
Min/Max Pins

The 8086 microprocessor can work in two modes of

operations :
 Minimum mode

 Maximum mode

In the Minimum mode of operation the microprocessor

do not associate with any co-processors and can not be
used for multiprocessor systems.

In the Maximum mode the 8086 can work in multi-

processor or co-processor configuration.

Minimum or maximum mode operations are decided by

the pin MN/MX(Active low).

When this pin is high 8086 operates in Minimum mode

otherwise it operates in Maximum mode.
Minimum mode signals

(Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor

used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
Minimum mode signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.
Maximum mode signals

Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.
Maximum mode signals

(Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.
Maximum mode signals
 Register Organisation of 8086
• The 8086 has a powerful set of registers

• It is also known as a programmer’s model of 8086.

• It contains
– General Purpose Registers

– Segment Registers

– Pointers and Index Registers

– Flag Register

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Register Organisation of 8086

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 Instruction Set of 8086
The instruction set of 8086 is divided into 8 major groups
• Data Movement Instructions

• Arithmetic and Logic Instructions

• String Instructions

• Program Control Transfer Instructions

• Iteration Control Instructions

• Processor Control Instructions

• External Hardware Synchronization Instructions

• Interrupt Instructions

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Timing Diagrams of
8086

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Read Operation in Minimum Mode

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Write Operation in Minimum Mode

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Read Operation in Maximum Mode

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Write Operation in Maximum Mode

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Interrupts of 8086

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 Interrupts
The event that causes interruption is called Interrupt and the
special routine executed to service the interrupt is called
Interrupt Service Routine/Procedure.
Normal Program can be interrupted by three ways:
 By External Signal
 By a special instruction in the program
 By the occurrence of some condition.

 An interrupt caused by an external signal is referred as a

Hardware Interrupts.
 Conditional interrupts or interrupts caused by special
instructions are called Software Interrupts.
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 Interrupt Cycle of 8086
 An 8086 interrupt can come from any one of the three sources:
External Signal
Special Instruction in the program
Condition produced by Instruction.

 External Signal (Hardware Interrupt)

 An 8086 can get interrupt from an external signal applied to

the Nonmaskable Interrupt (NMI) input pin, or the Interrupt

(INTR) input pin.

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 Special Instruction
 8086 supports a special instruction, INT to execute special
program. At the end of the Interrupt Service Routine, execution is
usually returned to the interrupted program.

 Condition produced by Instruction

 An 8086 is interrupted by some condition produced in the
8086 by the execution of an instruction.
 For example divide by zero:
Program execution will automatically be interrupted if
you attempt to divide operand by zero.
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• At the end of each instruction cycle 8086 checks to see if there
is any interrupt request.
• If so, 8086 responds to the interrupt by performing series of
actions. (Refer below figure)

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1. It decrements stack pointer by 2 and pushes flag register on the stack.
2. It disables the INTR interrupt input by clearing the interrupt flag in flag
register.
3. It resets the Trap flag in Flag register.
4. It decrements stack pointer by 2 and pushes current Code Segment (CS)
Register contents on the stack.
5. It decrements stack pointer by 2 and pushes current Instruction Pointer
(IP) contents on the stack.
6. It does an indirect far jump at the start of the procedure by loading CS and
IP values for the start of the Interrupt Service Routine (ISR).
An IRET instruction at the end of the Interrupt Service Procedure returns
execution to the Main Program.

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