ATPG Inputs

1) SCAN INSERTED NETLIST

2) LIBRARY FILES
3) TEST PROC FILE
 TETRAMAX FLOW

In Tetramax, There are three Modes Invoke Tool

1) BUILD-T
2) DRC-T
3) TEST-T BUILD-T

DRC-T

TEST-T
 TETRAMAX FLOW
BUILD-T DRC-T TEST-T

RUN DRC with

Invoke Tool SPF

Read SCAN No
Set ATPG settings
Netlist DRC

Generate
Read Libraries Ye
patterns
Fixs
DRC’s
Set BUILD settings coverage No Coverage
target
reached analysis
yes
RUN build model
Write patterns Write reports
 ATPG Issue’s

Inputs for ATPG are Library , Scan Inserted Netlist and SPF.
If you got any issues, May be one of the thing (lib / netlist / spf) might be the Issue

Invoke Tool

BUILD-T

DRC-T
If you got any issue in
this stage, It will be
because of Netlist
TEST-T
and Libraries not sync
 Invoke Tool

BUILD-T

DRC-T

TEST-T

-> The above error is build error. It caused because of module definition is missed.
Module Name is XOR2X1_HVT and it is instantanted by a name as clk_div_DW01_inc_0

-> By seeing that module name, It’s a library.

-> Now, You Want to search that module XOR2X1_HVT in all files at library directory
-> Once you got it. Read the file before “run_build_model”
 Invoke Tool
DRC Analysis -1 :

In Log or Command prompt, BUILD-T

-> You will see Begin Scan Design rules checking
-> Below Errors are (V17, V13)
+ V means vector rule DRC-T
++ V1
++ V2 etc..,,
-> To understand V17 or V13, Use “man V13” / “man V17” in the tool TEST-T
 Invoke Tool
man V13
BUILD-T

DRC-T

TEST-T
DRC Analysis - 1 :

Invoke Tool
Try to read Error twice
-> It is telling like, in “spf” Line 969. There is a problem related to “clk_500khz”.
clk_500khz should be pulsed not forced on BUILD-T

DRC-T

TEST-T
 Invoke Tool
DRC Analysis - 1 :
-> Open “spf” file BUILD-T

DRC-T

TEST-T
 Invoke Tool
DRC Analysis – 1 :
-> set line number in spf (Esc -> :set nu) BUILD-T

DRC-T

TEST-T
 Invoke Tool
DRC Analysis -1 :
->Go to that particular line showing Error BUILD-T
(In this case line number is 969)
-> Sometimes, It won’t show exact line number.
You need to dig before and after lines near to that DRC-T

TEST-T
 Invoke Tool
DRC Analysis - 1 :
->Go the definition where “_clk” is defined BUILD-T

DRC-T

TEST-T

During Shift, All resets should be inactive state

and clocks should be pulse

Hence : _clk = PP1 But, in shift “0P1”. Let us

change and give a run
 Invoke Tool
DRC Fixing - 1:
BUILD-T

DRC-T

TEST-T

After I changed “PP1” in shift also. I am getting same

errors.
Then I will dig indepth in “load_unload” procedure.

But one thing is clear, error is because of “clk_500khz”

 Invoke Tool
DRC Fixing - 1:
BUILD-T

But one thing is clear, error is because of “clk_500khz”

In “load_unload” procedure clk_500khz is used in DRC-T
“all_inputs” as well .
Check “clk_500khz“ is having off_state value or not
TEST-T

So, off_state value /

25th bit from starting initialise value is wrong.
Change to ‘0’ from ‘1’
 Invoke Tool
DRC Fixing -1 : Chains are successfully traced
And DRC doesn’t have Error’s
It enters into TEST-T mode BUILD-T

DRC-T

TEST-T
 Invoke Tool
DRC Analysis - 2:

All Scan Chains are blocked at 0th cell only BUILD-T

DRC-T

TEST-T
 Invoke Tool
DRC Analysis - 2:
-> Error or DRC is “S1” BUILD-T
-> Use “man S1” for help

DRC-T

TEST-T
 Invoke Tool
DRC Analysis – 2 :
-> Scan Chian is blocked at particular flop because of BUILD-T
+ Clock is not pulsing at that particular flop. You can control clock pulsing from “spf”
+ Reset / set / clear should be in-active state. You can control clock pulsing from “spf”
+ Scan Enable should be ‘1’ during Shifting DRC-T
+ Test Mode should be ‘1’
+ Scan chain path should be available in design (Q -> Si). You need to change design

-> You can use GUI

(Graphical User Interface for more details)
 Invoke Tool
DRC Analysis - 2: -> Click Analyze button

BUILD-T

Then it will open (Tetramax – Analyze window) DRC-T

TEST-T
 Invoke Tool
DRC Analysis - 2:
-> Select whatever violationyou want and click “ok” BUILD-T

DRC-T

TEST-T
 Invoke Tool
DRC Analysis - 2: -> After “ok”. You will see schematic window like below

BUILD-T

DRC-T

TEST-T
 Invoke Tool
DRC Analysis - 2:
-> Violation flop you will see in red color in schematic. Use zoom in and zoom out BUILD-T

-> Tracing will happens from back to front DRC-T

-> If you see fig, output (Q) is “sss” (shift shift shit)
-> Scan chain blockage issue is because of SI is “xxx”
+ Clock denotes “010” (before rising and after rising) TEST-T
+ Reset should be “111” (inactive state)
+ Scan Enable should be “111” during shifting

Scan Enable should be “1” during shifting. But its “xxx” instead of “111”. Trace back
 Invoke Tool
DRC Analysis - 2:
Trace back (double click)
BUILD-T

DRC-T

TEST-T

Trace back (double click)

• That flop Scan Enable is connected to top level “SCAN_EN”.

Which is not constrained / forced 1 during shifting. As it is a constrained. Forces will be in “spf”
 Invoke Tool
DRC Fixing- 2:
Open “spf” and check “SCAN_EN” value in “load_unload” procedure BUILD-T

DRC-T

SCAN_EN is missing TEST-T

Change and run again

 Invoke Tool
DRC Fixing - 2:

After I updated it, Now only two chains are blocked. BUILD-T

DRC-T

TEST-T

Inorder to check violations .use GUI. Analyse violations

 Invoke Tool
DRC Analysis - 2:

Output is “s00” instead of “sss”. BUILD-T

Check Flop inputs are correct or not

+ Clock Is pulsing “010” (Correct) DRC-T

+ Scan Enable is “111” (Correct)
+ Reset is in control state “111” (Wrong)
TEST-T

So, Now back trace it.

-> RSTB is connected to “reset_n”. But it is pulsing instead of “111”.
-> As it is a constrained, Either it has to come from tool or “spf”.
-> Wwe didn’t gave any constraints from tool. So, we need to check from “spf”
 Invoke Tool
DRC Analysis - 2:
BUILD-T
+ open “spf”. Go to load_unload procedure. Check reset value

DRC-T

TEST-T

+ From the above two figures, it is clear;ly showing reset_n is pulsing instead of forcing “1”.
+ Change reset should be “1” in “spf” and gave a run
 Invoke Tool
DRC Fixing - 2:
BUILD-T

DRC-T

TEST-T
 Invoke Tool
ATPG Settings and Pattern genenration
BUILD-T

DRC-T

Set the faults type : Report fault summary (Is just used
Stuckat to report faults before pattern TEST-T
Transition generation
bridging
path delay
Constraint on patterns /
coverage

Where you want to pattern

generation. If you want to Generate patterns (run_atpg)
generate patterns from Top
module onwords. Add faults for
all
Write patterns in “stil” format
 Invoke Tool
ATPG Settings and Pattern genenration
BUILD-T

DRC-T

Report Summaries before pattern generation:

TEST-T

Total faults : 692606

Fault mode : Stuckat
collapsed : No
Fault class : Detected faults (DI) are 125833
Test Coverage : 18.17 %
 Invoke Tool
ATPG Settings and Pattern genenration
BUILD-T

DRC-T

Pattern generation (run_atpg) :

+ It generated 100 patterns only because we told to tool generate only 100 TEST-T

+ There are different types of engines available in

Tetramax
++ run_atpg –auto / -auto_compression (Default)
++ run_atpg –opti / -optimise
++ run_atpg basic_scan_only
++ run_atpg fast_seq_atpg
++ run_atpg full_seq_atpg
 Invoke Tool
ATPG Settings and Pattern genenration
BUILD-T

DRC-T

Report Summaries after 100 pattern generation:

TEST-T

Total faults : 692606

Fault mode : Stuckat
collapsed : No
Fault class : Detected faults (DI) are 3189560
Test Coverage : 46.06%
Patterns : 100
 Invoke Tool
ATPG Settings and Pattern genenration
BUILD-T

DRC-T

Pattern generation without patterns constraints :

Tool is trying to give best coverage with best patterns TEST-T

Total faults : 692606

Fault mode : Stuckat
collapsed : No
Fault class : Detected faults (DI) are 665189
Test Coverage : 96.06%
Patterns : 8220
 Invoke Tool
ATPG Settings and Pattern genenration
BUILD-T
Coverage target reached?

DRC-T

TEST-T
Commerical applications Safety critical applications
Like Washing machine Like Defence, ISRO, aircraft,
TV etc.., Cars etc..,
Stuckat : ~= 98.5 to 99% Stuckat : ~= 99.5
Transition : ~= 80 to 85% Transition : ~= 90%
 Invoke Tool
ATPG Settings and Pattern genenration
BUILD-T
Coverage target reached?

No DRC-T

TEST-T
Coverage Analysis and Improvement
Coverage Analysis and Improvement
1) + When faults are not detected. First I will check this things.
++ review of tool constraints
++ Best algorithm in the tool like (run_atpg –auto , run_atpg –opti etc..)
++ Use latest tool version

2) + Report coverage like module wise. Check which module has low coverage
++ Use GUI (Graphical User Interface)
++ Use reports

3) + Increase tool effort by increasing abort limit

4) + Review atpg constraints like forces during capture. Remove if any unnecessary forces during capture.

5) + report non scan cells into one file

++ Open that file and check is there is any flops in the design
++ Try to understand, Why those flops are not in the scan chain. Is there is any SCAN DRC’s skipped
++ If those flops should be non scan. Then use fast seq or full seq atpg to improve coverage

6) + Generate reset patterns / clock patterns by removing constraints on capture mode

7) + Try to use different ATPG engine’s provided by EDA Vendors for better patterns with better coverage
Coverage Analysis and Improvement

Graphical User Interface (GUI)

Coverage Analysis and Improvement
Graphical User Interface (GUI)
-> Below window shows hierarchical browser
->> Top module dig_top has 96.07%
Coverage Analysis and Improvement

+ Test Coverage = Detected faults / Detectable faults

+ Fault Coverage = Detected faults / All faults
+ Test Coverage > Fault Coverage
+ By seeing above test coverage. Coverage is loosed because of AU faults are more at “u_apb_reg_2”
Coverage Analysis and Improvement
+ In u_apb_reg_2
instance, There are
25324 faults are there.
++ All modules are cells
inside that are only 4 AU
faults are there.
++ Its very difficult to
debug.
Coverage Analysis and Improvement

-> With the help of GUI, You can check where the coverage loss is there at some particular module.
-> If that module is analog module. Put that module in no-fault list
-> Then tool won’t add any faults on the module. Then coverage will be improve
Coverage Analysis and Improvement

-> Write out AU faults in the file

-> Open that file

Coverage Analysis and Improvement

-> report each and every fault why tool is not able to detect that
-> For example 1 :
sa0 AN clk_500khz
Coverage Analysis and Improvement
-> report each and every fault why tool is not able to detect that
-> For example 1 :
sa0 AN clk_500khz
Coverage Analysis and Improvement
-> report each and every fault why tool is not able to detect that
-> For example 1 :
sa0 AN clk_500khz
Coverage Analysis and Improvement
-> report each and every fault why tool is not able to detect that
-> For example 1 :
sa0 AN clk_500khz
Coverage Analysis and Improvement
-> For example 2 :
sa0 adc3_analog_in5 AN
Coverage Analysis and Improvement
-> For example 2 :
sa0 adc3_analog_in5 AN
Coverage Analysis and Improvement
-> For example 2 :
sa0 adc3_analog_in5 AN
Coverage Analysis and Improvement
-> For example 2 :
sa0 adc3_analog_in5 AN

+ adc0808 is an analog box. Hence we no need to add any faults on this module

+ because of black_box defined in script. Tool added faults around it.

+ Don’t define any black box. Just defined module
Coverage Analysis and Improvement

Coverage is improved from 96.06% to 96.09%

Coverage Analysis and Improvement

3) + Try to use abort limit increase and check coverage

“abort_limit” is nothing but, How tool is going to put effort on detecting fault
“set_atpg –abort_limit 300”

It increases coverage 96.09% to 96.10%

Coverage Analysis and Improvement