Computer Organization and

Architecture (AT70.01)
Comp. Sc. and Inf. Mgmt.
Asian Institute of Technology
Instructor: Dr. Sumanta Guha
Slide Sources: Patterson &
Hennessy COD book website
(copyright Morgan Kaufmann)
adapted and supplemented
COD Ch. 4
Arithmetic for Computers
Arithmetic
 Where we've been:
 performance
 abstractions
 instruction set architecture
 assembly language and machine language
 What's up ahead:
 implementing the architecture
operation

32 ALU
result
32
b

32
 Numbers
 Bits are just bits (no inherent meaning)
 conventions define relationship between bits and numbers
 Binary integers (base 2)
 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...

 decimal: 0, …, 2n-1 n bits

 Of course it gets more complicated:

 bit strings are finite, but
 for some fractions and real numbers, finitely many bits is not enough, so
 overflow & approximation errors: e.g., represent 1/3 as binary!
 negative integers
 How do we represent negative integers?
 which bit patterns will represent which integers?
 Possible Representations
 Sign Magnitude: One's Complement Two's Complement
000 = 0 000 = 0 000 = 0

ambiguous zero
001 = +1 001 = +1 001 = +1

ambiguous zero
010 = +2 010 = +2 010 = +2
011 = +3 011 = +3 011 = +3
100 = 0 100 = -3 100 = -4
101 = -1 101 = -2 101 = -3
110 = -2 110 = -1 110 = -2
111 = -3 111 = 0 111 = -1
 Issues:
 balance – equal number of negatives and positives
 ambiguous zero – whether more than one zero representation
 ease of arithmetic operations
 Which representation is best? Can we get both balance and non-ambiguous
zero?
Representation Formulae
 Two’s complement:

xn xn-1…x0 = xn * -2n + xn-1 * 2n-1 + … + x0 * 20

or
xnX’ = xn * -2n + X’ (writing rightmost n bits xn-1…x0 as X’)

= X’, if xn = 0
-2n + X’, if xn = 1

 One’s complement:

xnX’ = X’, if xn = 0
-2n + 1 + X’, if xn = 1
 MIPS – 2’s complement
 32 bit signed numbers:

0000 0000 0000 0000 0000 0000 0000 0000two = 0ten

0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten
0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten
maxint
...
0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten
0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten
1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten
...
1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten
1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten minint
1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

Negative integers are exactly those that have leftmost bit 1

Two's Complement Operations
 Negation Shortcut: To negate any two's complement integer
(except for minint) invert all bits and add 1
 note that negate and invert are different operations!
 why does this work? Remember we don’t know how to add in 2’s
complement yet! Later…!
 Sign Extension Shortcut: To convert an n-bit integer into an
integer with more than n bits – i.e., to make a narrow integer fill
a wider word – replicate the most significant bit (msb) of the
original number to fill the new bits to its left
 Example: 4-bit 8-bit
0010 = 0000 0010
1010 = 1111 1010
 why is this correct? Prove!
MIPS Notes
 lb vs. lbu
 signed load sign extends to fill 24 left bits
 unsigned load fills left bits with 0’s
 slt & slti
 compare signed numbers
 sltu & sltiu
 compare unsigned numbers, i.e., treat
both operands as non-negative
 Two’s Complement Addition
 Perform add just as in junior school (carry/borrow 1s)
 Examples (4-bits):
0101 0110 1011 1001 1111
0001 0101 0111 1010 1110
Do these sums now!! Remember all registers are 4-bit including result register!
So you have to throw away the carry-out from the msb!!
 Have to beware of overflow : if the fixed number of bits (4, 8, 16,
32, etc.) in a register cannot represent the result of the operation
 terminology alert: overflow does not mean there was a carry-out from
the msb that we lost (though it sounds like that!) – it means simply
that the result in the fixed-sized register is incorrect
 as can be seen from the above examples there are cases when the result
is correct even after losing the carry-out from the msb
 Two’s Complement Addition:
Verifying Carry/Borrow method
 Two (n+1)-bit integers: X = xnX’, Y = ynY’
Carry/borrow 0  X’ + Y’  2n 2n  X’ + Y’  2n+1 –
add X + Y (no CarryIn to last bit) 1
(CarryIn to last bit)
xn = 0, yn = 0 ok not ok(overflow!)
xn = 1, yn = 0 ok ok
xn = 0, yn = 1 ok ok
xn = 1, yn = 1 not ok(overflow!) ok

 Prove the cases above!

 Prove if there is one more bit (total n+2 then) available for the result
then there is no problem with overflow in add!
Two's Complement Operations
 Now verify the negation shortcut!
 consider X + (X +1) = (X + X) + 1:
associative law – but what if there is overflow in one of the adds on
either side, i.e., the result is wrong…!
 think minint !
 Examples:
 –0101 = 1010 + 1 = 1011
 –1100 = 0011 + 1 = 0100
 –1000 = 0111 + 1 = 1000
Detecting Overflow
 No overflow when adding a positive and a negative number
 No overflow when subtracting numbers with the same sign
 Overflow occurs when the result has “wrong” sign (verify!):

Operation Operand A Operand B Result

Indicating Overflow

A + B  0  0  0
A + B  0  0  0
A – B  0  0  0
A – B  0  0  0

 Consider the operations A + B, and A – B

 can overflow occur if B is 0 ?
 can overflow occur if A is 0 ?
Effects of Overflow
 If an exception (interrupt) occurs
 control jumps to predefined address for exception
 interrupted address is saved for possible resumption

 Details based on software system/language

 SPIM: see the EPC and Cause registers

 Don't always want to cause exception on overflow

 add, addi, sub cause exceptions on overflow
 addu, addiu, subu do not cause exceptions on overflow
 Review: Basic Hardware
1. AND gate (c = a . b) a b c=a.b
0 0 0
a
c 0 1 0
b
1 0 0
1 1 1

2. OR gate (c = a + b) a b c=a+b
0 0 0
a
c 0 1 1
b
1 0 1
1 1 1

3. Inverter (c = a) a c=a
a c 0 1
1 0

4. Multiplexor d d c
(if d = = 0, c = a;
else c = b) 0 a
a 0 1 b
c
b 1
Review: Boolean Algebra &
Gates
 Problem: Consider logic functions with three inputs: A, B, C.
 output D is true if at least one input is true
 output E is true if exactly two inputs are true
 output F is true only if all three inputs are true

 Show the truth table for these three functions

 Show the Boolean equations for these three
functions
 Show an implementation consisting of inverters,
AND, and OR gates.
 A Simple Multi-Function Logic
Unit
 To warm up let's build a logic unit to support the and and or
instructions for MIPS (32-bit registers)
 we'll just build a 1-bit unit and use 32 of them
operation
selector

a
output
b

 Possible implementation using a multiplexor :

Implementation with a
Multiplexor
 Selects one of the inputs to be the output
based on a control input

.
Operation .
.
a
0
Result
1
b

 Lets build our ALU using a MUX (multiplexor):

 Implementations
 Not easy to decide the best way to implement something
 do not want too many inputs to a single gate
 do not want to have to go through too many gates (= levels)
 for our purposes, ease of comprehension is important
 Let's look at a 1-bit ALU for addition:
CarryIn

cout = a.b + a.cin + b.cin

a

Sum sum = a.b.cin + a.b.cin +

b
a.b.cin + a.b.cin
= a  b  cin
CarryOut exclusive or (xor)

 How could we build a 1-bit ALU for add, and, and or?
 How could we build a 32-bit ALU?
 1-bit Adder Logic
xor

Half-adder with one xor gate

Full-adder from 2 half-adders and

an or gate

Half-adder with the xor gate replaced

by primitive gates using the equation
AB = A.B +A.B
 Building a 32-bit ALU
Multiplexor control line CarryIn Operation

Operation a0 CarryIn
Result0
CarryIn ALU0
b0
CarryOut
a
0
a1 CarryIn
Result1
1 ALU1
Result b1
CarryOut

2
b
a2 CarryIn
Result2
ALU2
b2
CarryOut CarryOut

1-bit ALU for AND, OR and add

a31 CarryIn
Result31
ALU31
b31

Ripple-Carry Logic for 32-bit ALU

What about Subtraction (a – b) ?
 Two's complement approach: just negate b and add.
 How do we negate?
 recall negation shortcut : invert each bit of b and set CarryIn to
least significant bit (ALU0) to 1
Binvert Operation
CarryIn

a
0

1
Result

b 0 2

CarryOut
Tailoring the ALU to MIPS:
Test

for Less-than and Equality
Need to support the set-on-less-than instruction
 e.g., slt $t0, $t3, $t4
 remember: slt is an R-type instruction that produces 1 if rs < rt
and 0 otherwise
 idea is to use subtraction: rs < rt  rs – rt < 0. Recall msb of
negative number is 1
 two cases after subtraction rs – rt:
 if no overflow then rs < rt  most significant bit of rs – rt = 1
 if overflow then rs < rt  most significant bit of rs – rt = 0
 why?
 e.g., 5ten – 6ten = 0101 – 0110 = 0101 + 1010 = 1111 (ok!)
-7ten – 6ten = 1001 – 0110 = 1001 + 1010 = 0011 (overflow!)
 therefore
set bit = msb of rs – rt  overflow bit
where set bit, which is output from ALU31, gives the result of slt
 Fig. 4.17(lower) indicates set bit is the adder output – not correct !!
 set bit is sent from ALU31 to ALU0 as the Less bit at ALU0; all other
Less bits are hardwired 0; so Less is the 32-bit result of slt
 Supporting slt
Binvert Operation
CarryIn

a
0 Binvert CarryIn Operation

Result a0 CarryIn
b 0 2 b0 ALU0 Result0
Less
1
CarryOut
Less input of
Less 3 the 31 most
significant ALUs
is always 0
a1 CarryIn
a. CarryOut
b1 ALU1 Result1
1- bit ALU for the 31 least significant bits 0 Less
Extra set bit, to be routed to the Less input of the least significant 1-bit CarryOut
ALU, is computed from the most significant Result bit and the Overflow bit
(it is not the output of the adder as the figure seems to indicate)
Binvert Operation
a2 CarryIn
CarryIn
b2 ALU2 Result2
0 Less
a CarryOut
0

Result CarryIn
b 0 2

1
a31 CarryIn Result31
Less 3 b31 ALU31 Set
0 Less Overflow
Set

Overflow
Overflow
detection
b.
32-bit ALU from 31 copies of ALU at top left and 1 copy
1-bit ALU for the most significant bit of ALU at bottom left in the most significant position
Tailoring the ALU to MIPS:
Test for Less-than and Equality
 What about logic for the overflow bit ?
 overflow bit = carry in to msb  carry out of msb
 verify!
 logic for overflow detection therefore can be put in to ALU31
 Need to support test for equality
 e.g., beq $t5, $t6, $t7
 use subtraction: rs - rt = 0  rs = rt
 do we need to consider overflow?
 Supporting ALU
control

Test for Equality lines

Bneg- Oper- Func-

Bnegate Operation
ate ation tion
a0
b0
CarryIn
ALU0
Result0 0 00 and
Less
CarryOut
0 01 or
Combine CarryIn
to least significant
0 10 add
ALU and Binvert to 1 10 sub
a single control line a1
1 11 slt
CarryIn Result1
as both are always b1 ALU1
either 1 or 0 0 Less
Zero
CarryOut

ALU operation

a2 CarryIn Result2
b2 ALU2 a
0 Less
CarryOut Output is 1 only if all Result bits are 0 Zero
ALU Result
Overflow
b

Result31 CarryOut
a31 CarryIn
b31 ALU31 Set
0 Less Overflow Symbol representing ALU

32-bit MIPS ALU

Conclusion
 We can build an ALU to support the MIPS instruction set
 key idea: use multiplexor to select the output we want
 we can efficiently perform subtraction using two’s complement
 we can replicate a 1-bit ALU to produce a 32-bit ALU
 Important points about hardware
 all gates are always working
 speed of a gate depends number of inputs (fan-in) to the gate
 speed of a circuit depends on number of gates in series
(particularly, on the critical path to the deepest level of logic)
 Speed of MIPS operations
 clever changes to organization can improve performance
(similar to using better algorithms in software)
 we’ll look at examples for addition, multiplication and division
 Problem: Ripple-carry Adder is
Slow
 Is a 32-bit ALU as fast as a 1-bit ALU? Why?
 Is there more than one way to do addition? Yes:
 one extreme: ripple-carry – carry ripples through 32 ALUs, slow!
 other extreme: sum-of-products for each CarryIn bit – super fast!
 CarryIn bits:
c1 = b0.c0 + a0.c0 + a0.b0 Note: ci is CarryIn bit into i th ALU;
c0 is the forced CarryIn into the
least significant ALU
c2 = b1.c1 + a1.c1 + a1.b1
= a1.a0.b0 + a1.a0.c0 + a1.b0.c0 (substituting for c1)
+ b1.a0.b0 + b1.a0.c0 + b1.b0.c0 + a1.b1

c3 = b2.c2 + a2.c2 + a2.b2

= … = sum of 15 4-term products…
 How fast? But not feasible for a 32-bit ALU! Why? Exponential complexity!!
 Two-level Carry-lookahead
Adder: First Level
 An approach between our two extremes
 Motivation:
 if we didn't know the value of a carry-in, what could we do?
 when would we always generate a carry? (generate) gi = ai . bi
 when would we propagate the carry? (propagate) pi = ai + bi

 Express (carry-in equations in terms of generate/propagates)

c1 = g0 + p0.c0
c2 = g1 + p1.c1 = g1 + p1.g0 + p1.p0.c0
c3 = g2 + p2.c2 = g2 + p2.g1 + p2.p1.g0 + p2.p1.p0.c0
c4 = g3 + p3.c3 = g3 + p3.g2 + p3.p2.g1 + p3.p2.p1.g0
+ p3.p2.p1.p0.c0
 Feasible for 4-bit adders – with wider adders unacceptable complexity.
 solution: build a first level using 4-bit adders, then a second level on top
Two-level Carry-lookahead
Adder: Second Level for a
16-bit adder
 Propagate signals for each of the four 4-bit adder blocks:
P0 = p3.p2.p1.p0
P1 = p7.p6.p5.p4
P2 = p11.p10.p9.p8
P3 = p15.p14.p13.p12

 Generate signals for each of the four 4-bit adder blocks:

G0 = g3 + p3.g2 + p3.p2.g1 + p3.p2.p1.g0
G1 = g7 + p7.g6 + p7.p6.g5 + p7.p6.p5.g4
G2 = g11 + p11.g10 + p11.p10.g9 + p11.p10.p9.g8
G3 = g15 + p15.g14 + p15.p14.g13 + p15.p14.p13.g12
Two-level Carry-lookahead
Adder: Second Level for a
16-bit adder
 CarryIn signals for each of the four 4-bit adder blocks (see
earlier carry-in equations in terms of generate/propagates):

C1 = G0 + P0.c0
C2 = G1 + P1.G0 + P1.P0.c0
C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.c0
C4 = G3 + P3.G2 + P3.P2.G1 + P3.P2.P1.G0 +
P3.P2.P1.P0.c0
 Carry-lookahead
C a r r y In

a0
b0
a1
b1
C a r r y In

4bAdder0
R e s u lt 0 - - 3 Logic
a2 CarryIn
P0
b2
a3
G0 Carry-lookahead Unit
b3
C1

a0

Logic to compute C1, C2, C3, C4

a4 C a r r y In
b4 ALU0
R e s u lt 4 - - 7 b0 s0

c1, c2, c3, c4, P0, G0

a5
b5 4bAdder1

Logic to compute
a6 P1
b6 a1 ALU1
a7
G1 s1
b7 b1
C2
a2 ALU2 s2
a8 C a r r y In b2
b8 R e s u lt 8 - - 1 1
a9 a3
b9 4bAdder2 ALU3 s3
a10 P2
b10 G2
b3
a11
b11
C3 Blow-up of 4-bit adder:
(conceptually) consisting of
a12
b12
C a r r y In
R e s u lt 1 2 - - 1 5
four 1-bit ALUs plus logic to
a13
b13 4bAdder3 compute all CarryOut bits
a14
b14
P3
G3
and one super generate and
a15
b15
C4 one super propagate bit.
C a rryO u t
Each 1-bit ALU is exactly as
16-bit carry-lookahead adder from four 4-bit for ripple-carry except c1, c2,
adders and one carry-lookahead unit c3 for ALUs 1, 2, 3 comes
from the extra logic
 Two-level Carry-lookahead
Adder: Second Level
for a 16-bit adder
 Two-level carry-lookahead logic steps:
1. compute pi’s and gi’s at each 1-bit ALU
2. compute Pi’s and Gi’s at each 4-bit adder unit
3. compute Ci’s in carry-lookahead unit
4. compute ci’s at each 4-bit adder unit
5. compute results (sum bits) at each 1-bit ALU
 E.g., add using carry-lookahead logic:
 0001 1010 0011 0011
 1110 0101 1110 1011
 Compare times for ripple-carry vs. carry-lookahead for a 16-bit
adder assuming unit delay at each gate
Multiply
 Grade school shift-add method:
Multiplicand 1000
Multiplier x 1001
1000
0000
0000
1000
Product 01001000
 m bits x n bits = m+n bit product
 Binary makes it easy:
 multiplier bit 1 => copy multiplicand (1 x multiplicand)
 multiplier bit 0 => place 0 (0 x multiplicand)
 3 versions of multiply hardware & algorithm:
 Shift-add Multiplier Version 1
Start

Multiplier0 = 1 1. Test Multiplier0 = 0

Multiplier0
32-bit multiplicand starts at right half of multiplicand register

Multiplicand 1a. Add multiplicand to product and

Shift left place the result in Product register
64 bits

Multiplier
64-bit ALU Shift right
2. Shift the Multiplicand register left 1 bit
32 bits

Product
Control test
Write 3. Shift the Multiplier register right 1 bit
64 bits

Product register is initialized at 0

No: < 32 repetitions
Multiplicand register, product register, ALU are 32nd repetition?

64-bit wide; multiplier register is 32-bit wide

Yes: 32 repetitions

Done Algorithm
 Shift-add Multiplier Version1
Start

Multiplier0 = 1 1. Test Multiplier0 = 0 Example: 0010 * 0011:

Multiplier0

Itera Step Multiplier Multiplicand Product

-tion
1a. Add multiplicand to product and
place the result in Product register
0 init 0011 0000 0010 0000 0000
values
1 1a 0011 0000 0010 0000 0010
2 0011 0000 0100 0000 0010
2. Shift the Multiplicand register left 1 bit
3 0001 0000 0100 0000 0010
2 …
3. Shift the Multiplier register right 1 bit

No: < 32 repetitions

32nd repetition?

Yes: 32 repetitions

Done

Algorithm
 Observations on Multiply
Version 1
 1 step per clock cycle  nearly 100 clock cycles to multiply two
32-bit numbers
 Half the bits in the multiplicand register always 0
 64-bit adder is wasted
 0’s inserted to right as multiplicand is shifted left
 least significant bits of product never
change once formed

 Intuition: instead of shifting multiplicand to left, shift product to

right…
 Shift-add Multiplier Version 2
Start

Multiplier0 = 1 1. Test Multiplier0 = 0

Multiplier0

Multiplicand 1a. Add multiplicand to the left half of

the product and place the result in
32 bits the left half of the Product register

Multiplier
32-bit ALU Shift right
32 bits 2. Shift the Product register right 1 bit

Shift right
Product Control test
Write
3. Shift the Multiplier register right 1 bit
64 bits

Product register is initialized at 0

No: < 32 repetitions
Multiplicand register, multiplier register, ALU 32nd repetition?

are 32-bit wide; product register is 64-bit wide; Yes: 32 repetitions

multiplicand adds to left half of product register
Done Algorithm
 Shift-add Multiplier Version 2
Start

Multiplier0 = 1 1. Test
Multiplier0
Multiplier0 = 0
Example: 0010 * 0011:

Itera Step Multiplier Multiplicand Product

1a. Add multiplicand to the left half of
the product and place the result in
-tion
the left half of the Product register 0 init 0011 0010 0000 0000
values
1 1a 0011 0010 0010 0000
2. Shift the Product register right 1 bit
2 0011 0010 0001 0000
3 0001 0010 0001 0000

3. Shift the Multiplier register right 1 bit

2 …

No: < 32 repetitions

32nd repetition?

Yes: 32 repetitions

Done

Algorithm
Observations on Multiply
Version 2

 Each step the product register wastes space that exactly matches
the current size of the multiplier

 Intuition: combine multiplier register and product register…

 Shift-add Multiplier Version 3
Start

Product0 = 1 1. Test Product0 = 0

Product0

Multiplicand

32 bits 1a. Add multiplicand to the left half of

the product and place the result in
the left half of the Product register

32-bit ALU

Shift right Control 2. Shift the Product register right 1 bit

Product
Write test
64 bits

No: < 32 repetitions

32nd repetition?
Product register is initialized with multiplier on right

No separate multiplier register; multiplier

Yes: 32 repetitions

placed on right side of 64-bit product register

Done Algorithm
 Shift-add Multiplier Version 3
Start

Product0 = 1 1. Test Product0 = 0

Product0 Example: 0010 * 0011:

Itera Step Multiplicand Product

-tion
1a. Add multiplicand to the left half of
the product and place the result in
0 init 0010 0000 0011
the left half of the Product register values
1 1a 0010 0010 0011
2 0010 0001 0001
2 …
2. Shift the Product register right 1 bit

No: < 32 repetitions

32nd repetition?

Yes: 32 repetitions

Done

Algorithm
 Observations on Multiply
Version 3
 2 steps per bit because multiplier & product combined
 What about signed multiplication?
 easiest solution is to make both positive and remember whether to
negate product when done, i.e., leave out the sign bit, run for 31 steps,
then negate if multiplier and multiplicand have opposite signs

 Booth’s Algorithm is an elegant way to multiply signed numbers using

same hardware – it also often quicker…
 Motivating Booth’s algorithm
 Example 0010 * 0110. Traditional:
0010
x 0110
0000 shift (0 in multiplier)
0010 add (1 in multiplier)
0010 add (1 in multiplier)
0000 shift (0 in multiplier)
00001100
 Same example. But observe there are two successive 1’s in multiplier
0110 = 22 + 21 = 23 – 21, so can replace successive 1’s by subtract and
then add:
0010
0110
0000 shift (0 in multiplier)
-0010 sub (first 1 in multiplier)
0000 shift (middle of string of 1’s)
0010 add (previous step had last 1)
00001100
 Motivating Booth’s Algorithm
middle of run
end of run beginning of run
0 1 1 1 1 0
bit = 2n bit = 2m

 Math idea: string of 1’s …011…10… has

successive 1’s

value the sum 2n + 2n-1 + … + 2m = 2n+1 – 2m

 Replace a string of 1s in multiplier with an initial subtract when we

first see a one and then later add after the last one
 What if the string of 1’s started from the left of the (2’s complement) number,
e.g., 11110001 – would the formula above have to be modified?!
 Booth from Multiply Version 3
 Modify Step 1 of the algorithm Multiply Version 3 to consider 2 bits of
the multiplier: the current bit and the bit to the right (i.e., the current
bit of the previous step). Instead of two outcomes, now there are four:

Case Current Bit Bit to the Right Explanation Example Op

1a 0 0 Middle of run of 0s 0001111000 none
1b 0 1 End of run of 1s 0001111000 add
1c 1 0 Begins run of 1s 0001111000 sub
1d 1 1 Middle of run of 1s 0001111000 none

 Modify Step 2 of Multiply Version 3 to sign extend when the product is

shifted right (arithmetic right shift, rather than logical right shift)
because the product is a signed number
 Now draw the flowchart for Booth’s algorithm !
 Multiply Version 3 and Booth share the same hardware, except Booth
requires one extra flipflop to remember the bit to the right of the
current bit in the product register – which is the bit pushed out by the
preceding right shift
 Booth Example (2 x 7)
Operation Multiplicand Product next?
0. initial value 0010 0000 0111 0 10 -> sub P = P - M

1c. 0010 1110 0111 0 shift P (sign ext)

2. 0010 1111 0011 1 11 -> nop
1d. 0010 1111 0011 1 shift P (sign ext)
2. 0010 1111 1001 1 11 -> nop
1d. 0010 1111 1001 1 shift P (sign ext)
2. 0010 1111 1100 1 01 -> add P = P + M
1b. 0010 0001 1100 1 shift P (sign ext)
2. 0010 0000 1110 0 done
 Booth Algorithm (2 * -3)
Operation Multiplicand Product next?
0.initial value 0010 0000 1101 0 10 -> sub P = P - M
1c. 0010 1110 1101 0 shift P (sign ext)
2. 0010 1111 0110 1 01 -> add P = P + M
1b. 0010 0001 0110 1 shift P (sign ext)
2. 0010 0000 1011 0 10 -> sub P = P - M
1c. 0010 1110 1011 0 shift P
2. 0010 1111 0101 1 11 -> nop
1d. 0010 1111 0101 1 shift P
2. 0010 1111 1010 1 done
Verifying Booth’s Algorithm
 multiplier a = a31 a32… a0, multiplicand = b
 ai ai-1 Operation
0 0 nop
0 1 add b
1 0 sub b
1 1 nop
 0, nop
I.e., if ai-1 – ai = +1, add b
–1, sub b
 Therefore, Booth computes sum:
(a–1 – a0) * b * 20
+ (a0 – a 1) * b * 21
+ (a1 – a2) * b * 22
…
+ (a30 – a31) * b * 231
= … simplify telescopic sum! …
MIPS Notes
 MIPS provides two 32-bit registers Hi and Lo to hold a 64-bit
product
 mult, multu (unsigned) put the product of two 32-bit register
operands into Hi and Lo: overflow is ignored by MIPS but can
be detected by programmer by examining contents of Hi
 mflo, mfhi moves content of Hi or Lo to a general-purpose
register
 Pseudo-instructions mul (without overflow), mulo (with
overflow), mulou (unsigned with overflow) take three 32-bit
register operands, putting the product of two registers into the
third
 Divide
1001 Quotient
Divisor 1000 1001010 Dividend
–1000
10
101
1010
–1000
10 Remainder

 Junior school method: see how big a multiple of the divisor can be
subtracted, creating quotient digit at each step
 Binary makes it easy  first, try 1 * divisor; if too big, 0 * divisor
 Dividend = (Quotient * Divisor) + Remainder
 3 versions of divide hardware & algorithm:
 Start

Divide Version 1 1. Subtract the Divisor register from the

Remainder register and place the
result in the Remainder register

32-bit divisor starts at left half of divisor register

Remainder –> 0 Remainder < 0

Test Remainder
Divisor Quotient register is
Shift right
initialized to be 0
64 bits

2a. Shift the Quotient register to the left, 2b. Restore the original value by adding
Quotient setting the new rightmost bit to 1 the Divisor register to the Remainder
64-bit ALU Shift left register and place the sum in the
32 bits Remainder register. Also shift the
Quotient register to the left, setting the
new least significant bit to 0
Remainder Control
Write test
64 bits

3. Shift the Divisor register right 1 bit

Remainder register is initialized with the dividend at right

Divisor register, remainder register, ALU are 33rd repetition?

No: < 33 repetitions

64-bit wide; quotient register is 32-bit wide

Yes: 33 repetitions

Why 33? We shall see later… Done Algorithm

 Divide Version 1
Start

Example: 0111 / 0010:

1. Subtract the Divisor register from the
Remainder register and place the
result in the Remainder register
Itera- Step Quotient Divisor Remainder
tion
0 init 0000 0010 0000 0000 0111
Remainder –> 0 Remainder < 0
1 1 0000 0010 0000 1110 0111
Test Remainder
2b 0000 0010 0000 0000 0111
3 0000 0001 0000 0000 0111

2a. Shift the Quotient register to the left, 2b. Restore the original value by adding
2 …
setting the new rightmost bit to 1 the Divisor register to the Remainder 3
register and place the sum in the
Remainder register. Also shift the 4
Quotient register to the left, setting the
new least significant bit to 0 5

3. Shift the Divisor register right 1 bit

No: < 33 repetitions

33rd repetition?

Yes: 33 repetitions

Done Algorithm
 Observations on Divide Version 1
 Half the bits in divisor always 0
  1/2 of 64-bit adder is wasted

  1/2 of divisor register is wasted

 Intuition: instead of shifting divisor to right, shift remainder to left…

 Step 1 cannot produce a 1 in quotient bit – as all bits corresponding

to the divisor in the remainder register are 0 (remember all operands
are 32-bit)
 Intuition: switch order to shift first and then subtract – can save 1
iteration…
 Divide Version 2
Start

1. Shift the Remainder register left 1 bit

Divisor Remainder register is initialized 2. Subtract the Divisor register from the
left half of the Remainder register and
with the dividend at right place the result in the left half of the
32 bits
Remainder register

Quotient
32-bit ALU Shift left
Remainder >
– 0 Remainder < 0
32 bits Test Remainder

Shift left Control

Remainder
Write test
64 bits
3a. Shift the Remainder register to the 3b. Restore the original value by adding
left, setting the new rightmost bit to 0. the Divisor register to the left half of the
Also shift the Quotient register to the left Remainder register and place the sum
setting to the new rightmost bit to 1. in the left half of the Remainder register.
Divisor register, quotient register, Also shift the Remainder register to the
left, setting the new rightmost bit to 0
ALU are 32-bit wide; remainder Also shift the Quotient register to the left
setting to the new rightmost bit to 0.
register is 64-bit wide

No: < 32 repetitions

32nd repetition?

Yes: 32 repetitions

Why this correction step? We shall see later… Algorithm

Done. Shift left half of Remainder right 1 bit
 Observations on Divide Version 2

 Each step the remainder register wastes space that exactly matches
the current size of the quotient

 Intuition: combine quotient register and remainder register…

 Start

Divide Version 3 1. Shift the Remainder register left 1 bit

2. Subtract the Divisor register from the

left half of the Remainder register and
place the result in the left half of the
Remainder register

Divisor
Remainder >
– 0 Remainder < 0
32 bits Test Remainder

32-bit ALU
3a. Shift the Remainder register to the 3b. Restore the original value by adding
left, setting the new rightmost bit to 1 the Divisor register to the left half of the
Remainder register and place the sum
Shift right in the left half of the Remainder register.
Remainder Control Also shift the Remainder register to the
Shift left
test left, setting the new rightmost bit to 0
Write
64 bits

Remainder register is initialized with the dividend at right

No separate quotient register; quotient
No: < 32 repetitions
32nd repetition?

is entered on the right side of the 64-bit

remainder register Yes: 32 repetitions
Algorithm
Why this correction step? We shall see later… Done. Shift left half of Remainder right 1 bit
 Divide Version 3
Start

Example: 0111 / 0010:

1. Shift the Remainder register left 1 bit

Itera- Step Divisor Remainder

2. Subtract the Divisor register from the tion
left half of the Remainder register and 0 init 0010 0000 0111
place the result in the left half of the
Remainder register 1 0010 0000 1110
1 2 0010 1110 1110
3b 0010 0001 1100
Remainder >
– 0
Test Remainder
Remainder < 0
2 …
3
4
3a. Shift the Remainder register to the 3b. Restore the original value by adding
left, setting the new rightmost bit to 1 the Divisor register to the left half of the
Remainder register and place the sum
in the left half of the Remainder register.
Also shift the Remainder register to the
left, setting the new rightmost bit to 0

No: < 32 repetitions

32nd repetition?

Yes: 32 repetitions

Done. Shift left half of Remainder right 1 bit Algorithm

 Number of Iterations
 Why the extra iteration in Version 1?
 Why the final correction step in Versions 2 & 3?
Ovals represent loop iterations
Main insight – sub(i+1) must actually follow shifti of
the divisor (or remainder, depending on version) and
Shift: see the version descriptions the resulting bit in the quotient appears on shift(i+1)
for which registers are shifted

shift1 shift2 … shift32 shift33

sub1 sub2 sub3 … sub32 sub33

V1 starts loop One loop iteration

Critical situation! Only the quotient shift is
here: unnecessary necessary as it corresponds to the
sub step V2 & 3 start outcome of the previous sub.
loop here So V1 is ok even though the last divisor
shift is redundant, as final divisor is ignored
V2 & 3 initial step:
any way; V2 & 3 must repair remainder
before loop starts as it has shifted left one time too many
Observations on Divide Version 3
 Same hardware as Multiply Version 3

 Signed divide:
 make both divisor and dividend positive and perform division
 negate the quotient if divisor and dividend were of opposite signs
 make the sign of the remainder match that of the dividend
 this ensures always
 dividend = (quotient * divisor) + remainder
 –quotient (x/y) = quotient (–x/y) (e.g. 7 = 3*2 + 1 & –7 = –3*2 – 1)
MIPS Notes
 div (signed), divu (unsigned), with two 32-bit register
operands, divide the contents of the operands and put
remainder in Hi register and quotient in Lo; overflow is ignored
in both cases

 pseudo-instructions div (signed with overflow), divu

(unsigned without overflow) with three 32-bit register operands
puts quotients of two registers into third
 Floating Point
 We need a way to represent
 numbers with fractions, e.g., 3.1416
 very small numbers (in absolute value), e.g., .00000000023
 very large numbers (in absolute value) , e.g., –3.15576 * 1046
 Representation:
binary point
 scientific: sign, exponent, significand form:
 (–1)sign * significand * 2exponent . E.g., –101.001101 * 2111001
 more bits for significand gives more accuracy
 more bits for exponent increases range
 if 1  significand  10two(=2ten) then number is normalized, except
for number 0 which is normalized to significand 0
 E.g., –101.001101 * 2111001 = –1.01001101 * 2111011 (normalized)
 IEEE 754 Floating-point Standard
 IEEE 754 floating point standard:
 single precision: one word
31 bits 30 to 23 bits 22 to 0

sign 8-bit exponent 23-bit significand

 double precision: two words

31 bits 30 to 20 bits 19 to 0

sign 11-bit exponent upper 20 bits of 52-bit significand

bits 31 to 0

lower 32 bits of 52-bit significand

IEEE 754 Floating-point Standard
 Sign bit is 0 for positive numbers, 1 for negative numbers

 Number is assumed normalized and leading 1 bit of significand left of

binary point (for non-zero numbers) is assumed and not shown
 e.g., significand 1.1001… is represented as 1001…,
 exception is number 0 which is represented as all 0s (see next slide)
 for other numbers:
value = (–1)sign * (1 + significand) * 2exponent value

 Exponent is biased to make sorting easier

 all 0s is smallest exponent, all 1s is largest
 bias of 127 for single precision and 1023 for double precision
equals exponent value
 therefore, for non-0 numbers:
value = (–1)sign * (1 + significand) * 2(exponent – bias)
IEEE 754 Floating-point Standard
 Special treatment of 0:
 if exponent is all 0 and significand is all 0, then the value is
0 (sign bit may be 0 or 1)
 if exponent is all 0 and significand is not all 0, then the value is
(–1)sign * (1 + significand) * 2-127
 therefore, all 0s is taken to be 0 and not 2-127 (as would be for a non-zero
normalized number); similarly, 1 followed by all 0’s is taken to be 0 and not
- 2-127

 Example : Represent –0.75ten in IEEE 754 single precision

 decimal: –0.75 = –3/4 = –3/22
 binary: –11/100 = –.11 = –1.1 x 2-1
 IEEE single precision floating point exponent = bias + exponent value
= 127 + (-1) = 126ten = 01111110two
 IEEE single precision: 10111111010000000000000000000000
exponent significand
sign
 Start

Floating Point 1. Compare the exponents of the two numbers.

Addition
Shift the smaller number to the right until its
exponent would match the larger exponent

2. Add the significands

 Algorithm: 3. Normalize the sum, either shifting right and

incrementing the exponent or shifting left
and decrementing the exponent

Overflow or Yes
underflow?

No
Exception

4. Round the significand to the appropriate

number of bits

No
Still normalized?

Yes

Done
Floating Point
Addition Sign Exponent Significand Sign Exponent Significand

Compare
Small ALU exponents
 Hardware:
Exponent
difference

0 1 0 1 0 1

Shift smaller
Control Shift right
number right

Add
Big ALU

0 1 0 1

Increment or
decrement Shift left or right Normalize

Rounding hardware Round

Sign Exponent Significand

 Start

Floating Point 1. Add the biased exponents of the two

numbers, subtracting the bias from the sum

Multpication
to get the new biased exponent

2. Multiply the significands

 Algorithm: 3. Normalize the product if necessary, shifting

it right and incrementing the exponent

Overflow or Yes
underflow?

No
Exception

4. Round the significand to the appropriate

number of bits

No
Still normalized?

Yes

5. Set the sign of the product to positive if the

signs of the original operands are the same;
if they differ make the sign negative

Done
Floating Point Complexities
 In addition to overflow we can have underflow (number too
small)
 Accuracy is the problem with both overflow and underflow
because we have only a finite number of bits to represent
numbers that may actually require arbitrarily many bits
 limited precision  rounding  rounding error
 IEEE 754 keeps two extra bits, guard and round
 four rounding modes
 positive divided by zero yields infinity
 zero divide by zero yields not a number
 other complexities
 Implementing the standard can be tricky
 Not implementing the standard can be even worse
 see text for discussion of Pentium bug!
MIPS Floating Point
 MIPS has a floating point coprocessor (numbered 1, SPIM) with
thirty-two 32-bit registers $f0 - $f31. Two of these are required
to hold doubles. Floating point instructions must use only even-
numbered registers (including those operating on single floats).
SPIM simulates MIPS floating point.

 Floating point arithmetic: add.s (single addition), add.d

(double addition), sub.s, sub.d, mul.s, mul.d, div.s,
div.d

 Floating point comparison: c.x.s (single), c.x.d (double),

where x may be eq, neq, lt, le, gt, ge

 Other instructions…
Summary
 Computer arithmetic is constrained by limited precision
 Bit patterns have no inherent meaning but standards do exist:
 two’s complement
 IEEE 754 floating point
 Computer instructions determine meaning of the bit patterns.
 Performance and accuracy are important so there are many
complexities in real machines (i.e., algorithms and
implementation)

 Read Computer Arithmetic Algorithms by I. Koren

 it is easy-to-read and shows new algorithms for arithmetic
 there will be assignment and projects based on Koren’s material