Voltage Limitations

A MOSFET experiences various undesirable effects if its terminal

voltage differences exceed certain limits (if the device is “stressed”).
At high gate-source voltages, the gate oxide breaks down irreversibly,
damaging the transistor.
In short-channel devices, an excessively large drain-source voltage
widens the depletion region around the drain so much that it touches
that around the source, creating a very large drain current.
(This effect is called “punchthrough”).
Even without breakdown, MOSFETs’ characteristics can change
permanently if the terminal voltage differences exceed a specified
value. Such effects are described in Chapter 17.

1
MOS Device Models MOS Device Layout
W/L is chosen to set the transconductance or other circuit parameters
The minimum L is dictated by the process.
In addition to the gate, the source and drain areas must be defined
properly as well.
one or more “contact windows” must
be opened in each region,

Example 2.9
Draw the layout of the circuit shown in Fig. 2.30(a).

2
MOS Device Capacitances

Decomposition of S/D junction

capacitance into bottom-plate and
sidewall components.

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(1) the oxide capacitance between the gate and the channel,
C1 = WLCox;
(2) the depletion capacitance between the channel and the substrate,
C2 = WL √qϵsi Nsub/(4φF ); and
(3) the capacitance due to the overlap of the gate poly with the source
and drain areas, C3 and C4. Owing to fringing electric field lines, C3
and C4 cannot be simply written as WLDCox, and are usually obtained
by more elaborate calculations. The overlap capacitance per unit
width is denoted by Cov and expressed in F/m (or fF/μm).We simply
multiply Cov by W to find the gate-source and gate-drain overlap
capacitances.
(4) The junction capacitance between the source/drain areas and the
substrate. As shown in Fig. 2.32(b), this last capacitance is
decomposed into two components:

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the bottom-plate capacitance associated with the bottom of the
junction, Cj , and the sidewall capacitance due to the perimeter of
the junction, Cjsw.
The distinction is necessary because different transistor geometries
yield different area and perimeter values for the S/D junctions.
We specify Cj and Cjsw as capacitance per unit area (in F/m2) and unit
length (in F/m), respectively.
Thus, Cj is multiplied by the S/D area, and Cjsw by the S/D perimeter.
Note that each junction capacitance can be expressed as
Cj = Cj0/[1 + VR/(φB)]m, where VR is the reverse voltage across the
junction, φB is the junction built-in potential, and m is a power
typically in the range of 0.3 and 0.4.

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6
Example 2.10 Calculate the source and drain junction capacitances of
the two structures shown in Fig. 2.33.

Fig. 2.33(b) exhibits less

drain junction capacitance
than that in Fig. 2.33(a) while
providing the same W/L.
“folded” structure

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If the device is off, CGD = CGS = CovW, and
the gate-bulk capacitance consists of the series combination of the
gate-oxide capacitance and the depletion-region capacitance
[Fig.2.32(a)], i.e

If the device is in the deep triode region, i.e., if S and D have Permittivity
approximately equal voltages, then the gate-channel capacitance,
WLCox, is divided equally between the gate and source terminals and
the gate and drain terminals (Fig. 2.34). This is because a change of
ΔV in the gate voltage draws equal amounts of charge from S and D.
Thus,

8
Let us now consider CGD and CGS.
If in saturation, a MOSFET exhibits a gate-drain capacitance roughly
equal to WCov.
As for CGS, we note that the potential difference between the gate
and the channel varies from VGS at the source to VTH at the pinch-off
point,
resulting in a nonuniform vertical electric field in the gate oxide as we
travel from the source to the drain.
It can be proved that the equivalent capacitance of this structure,
excluding the gate-source overlap capacitance, equals (2/3)WLCox .
Thus, CGS = 2WLeffCox/3+WCov.
The behavior of CGD and CGS in different regions of operation is plotted
in Fig. 2.34

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Note that the above equations do not provide a smooth transition
from one region of operation to another, creating convergence
difficulties in simulation programs.
This issue is revisited in Chapter 17.
The gate-bulk capacitance is usually neglected in the triode and
saturation regions because the inversion layer acts as a “shield”
between the gate and the bulk.
In other words, if the gate voltage varies, the charge is supplied by the
source and the drain rather than the bulk.

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Example 2.11
Sketch the capacitances of M1 in Fig. 2.35 as VX varies from zero to 3 V.
Assume that VTH = 0.3 V and λ = γ = 0.

and CFB is maximum

The value of CNB is independent of VX.
As VX exceeds 1 V, the role of the source and drain is
exchanged [Fig. 2.36(a)], eventually bringing M1 out
of the triode region for VX ≥ 2 V−0.3 V. The variation of the
capacitances is plotted in Figs. 2.36(b) and (c).

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MOS Small-Signal Model
We derive the small-signal model by producing a small increment in
one bias parameter and calculating the resulting increment in other
bias parameters.Specifically, we
(1) apply certain bias voltages to the terminals of the device,
(2) increment the potential difference between two of the terminals
while other terminal voltages remain constant, and
(3) measure the resulting change in all terminal currents.
Let us apply a change to the gate-source voltage, ΔV = VGS, where VGS
is a small-signal quantity.
The drain current therefore changes by gmVGS
Owing to channel-length modulation, the drain
current also varies with the drain-source voltage.

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MOS Small-Signal Model

A current source whose value

linearly depends on the voltage
across it is equivalent to a linear
resistor ro

where it is assumed that λVDS << 1

Output resistance, rO , is important ?
affects the performance of many analog circuits

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Now recall that the bulk potential influences the threshold voltage and
hence the gate-source overdrive.
That is, the bulk behaves
as a second gate.
In the saturation region, gmb can be
expressed as

typically
around 0.25.
incremental body effect becomes
less pronounced as VSB increases.

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We note that folding reduces the gate resistance by a factor of four.

15
Shown in Fig. 2.39, the complete small-signal model includes the
device capacitances as well.

16
Example 2.12
Sketch gm and gmb of M1 in Fig. as a function of the bias current I1.

The dependence of gmb upon I1 is less straightforward. As I1 increases,

VX decreases, and so does VSB.

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PMOS Small-Signal Model

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19
20
NMOS Versus PMOS Devices
In most CMOS technologies, PMOS devices are quite inferior to NMOS
transistors.
For example, due to the lower mobility of holes,
μpCox ≈ 0.5μnCox, yielding low current drive and transconductance.
Moreover, for given dimensions and bias currents, NMOS transistors
exhibit a higher output resistance, providing more ideal current
sources and higher gain in amplifiers.
For these reasons, incorporating NFETs rather than PFETs wherever
possible is preferred.

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Long-Channel Versus Short-Channel Devices
In this chapter, we have employed a very simple view of MOSFETs so
as to understand the basic principles of their operation.
Most of our treatment is valid for “long-channel” devices, e.g.,
transistors having a minimum length of a few microns.
Many of the relationships derived here must be reexamined and
revised for short-channel MOSFETs.
Furthermore, the SPICE models necessary for simulation of today’s
devices are much more sophisticated than the Level 1 model.
For example, the intrinsic gain, gmrO, calculated from the device
parameters in Table 2.1 is much higher than actual values.
These issues are studied in Chapter 17.
We begin with a simplistic view of devices.
The key point is that the simple model provides a great deal of
intuition that is necessary in analog design.
We often encounter a trade-off between intuition and rigor, and our
approach is to establish the intuition first and gradually complete our
understanding so as to achieve rigor as well. 22
FinFETs
This device exhibits superior
performance as channel lengths fall
below approximately 20 nm.
In fact, FinFET I/V characteristics
are closer to square-law behavior,
making our simple large-signal
mode relevant again.
The equivalent channel width is
therefore equal to the sum of the fin’s
width, WF , and twice its height, HF :
W = WF +2HF .
Typically, WF ≈ 6 nm and HF ≈ 50 nm.

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Behavior of a MOS Device as a Capacitor
Inversion layer begins to form for VGS ≈ VTH.
We also noted that for 0 < VGS < VTH, the
device operates in the subthreshold region.

Let us begin with a very negative gate-source voltage.

As VGS rises, the density of holes at the
interface falls, a depletion region begins to
form under the oxide, and the device enters
weak inversion.
In this mode, the capacitance consists of the
series combination of Cox and Cdep.
Finally, as VGS exceeds VTH, the oxide-silicon
interface sustains a channel and the unit-area
capacitance returns to Cox. Figure 2.46 plots
the behavior.
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Single-Stage Amplifiers Define amplifier?

An ideal amplifier generates an output, y(t), that is a linear replica of

the input, x(t): y(t) = α1x(t)

25
 y(t) = α0 + α1x(t)
y(t) = α0 + α1x(t) + α2x2(t) +・ ・ ・+ αnxn(t)

What aspects of the performance of an amplifier are important?

a. In addition to gain and c. Supply e. Noise, or
speed, voltage, f. Max voltage
b. power dissipation, d. Linearity, swings
Input and output impedances determine how the circuit interacts
with the preceding and subsequent stages.

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In practice, most of these parameters trade with each other, making
the design a multidimensional optimization problem.
“analog design octagon”

27
(1) Set up proper bias conditions so that each transistor provides the
necessary transconductance and output resistance with certain
quiescent currents and voltages, and
(2) Analyze the circuit’s behavior as the input and output signals
cause small or large departures from the bias input (small-signal
and large-signal analyses, respectively).

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 Common-Source Stage with Resistive Load
Input voltage is zero, M1 is off and Vout = VDD .
As Vin approaches VTH, M1 begins to turn on, drawing current from
RD and lowering Vout .
Transistor M1 turns on in saturation regardless of the values of VDD
and RD (why?)

until Vin exceeds Vout by VTH

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 deep triode region

transconductance drops

ensure that Vout > Vin − VTH

30
M1 converts ΔVin to a drain current change gmΔVin
Then output voltage change −gm RD ΔVin.
The small-signal model yields

Vout = −gmV1RD = −gmVin RD.

Av = −gm RD predicts certain effects in case of a large signal swing
Since gm itself varies with the input signal according to
gm = μnCox (W/L)(VGS − VTH)
the gain of the circuit changes substantially if the signal is large.
the circuit operates in the large-signal mode.
This dependence of the gain leads to nonlinearity.
minimize the nonlinearity
gain equation must be a weak function of gm

31
Example 3.1 Sketch the drain current and transconductance of M1 in
Fig. 3.4(a) as a function of the input voltage.
The drain current becomes significant for Vin > VTH
approaching VDD/RD if Ron1 << RD .
In saturation,
gm = μnCox (W/L)(Vin − VTH),
the transconductance begins to rise
for Vin > VTH.
In triode region, gm = μnCox (W/L)VDS,
falls as Vin exceeds Vin1 . Starting with Eq. (3.5)

Reaches a maximum if Vout = Vin − VTH (point A).

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Example 3.2
A CS stage is driven by a sinusoid, Vin = V1 cos ω1t +V0, where V0 is the
bias value and V1 is large enough to drive the transistor into the off and
triode regions. Sketch the gm of the transistor as a function of time.
When Vin = V1 + V0 , Vout is low, M1 is in the
triode region,
and gm assumes a small value.
As Vin falls and Vout and gm rise, M1 enters
saturation at t = t1
(when Vin − Vout = VTH) and gm reaches its
maximum (why?).
As Vin falls further, so do ID and gm.
At t = t2, gm reaches zero.

33
We observe that (a) voltage gain is approximately equal to −gm RD, it
experiences the same variation as the gm, and
(b) gm varies periodically.
We even express gm as a Fourier series in more advanced courses.

34
How do we maximize the voltage gain of a common-source stage?

where VRD denotes the voltage drop across RD,

A larger device size leads to greater device capacitances,
A higher VRD limits the maximum voltage swings.
If VDD−VRD = Vin−VTH, then M1 is at the edge of the triode region,
If VRD remains constant and ID is reduced, then RD must increase,
thereby leading to a greater time constant at the output node.
In other words, as noted in the analog design octagon, the circuit
exhibits trade-offs between gain, bandwidth, and voltage swings.
Lower supply voltages further tighten these trade-offs.

35
For large values of RD, the effect of channel-length modulation in
M1 becomes significant.

36
 Example 3.3 Assuming that M1 in Fig. 3.8 is biased in saturation,
calculate the small-signal voltage gain of the circuit.
Since I1 introduces an infinite impedance (RD =∞),
gain is limited by the output resistance of M1:
Called the “intrinsic gain” of a transistor, this quantity
represents the maximum voltage gain that can be
achieved using a single device.
In today’s CMOS technology, gmrO of short-channel devices is between
roughly 5 and 10.
ID1 = I1. Then, how can Vin change the current of M1 if I1 is constant?
As Vin increases, Vout must
decrease to keep I1 constant.
“ID1 increases as Vin increases.” It simply refers to the quadratic part.
To maximize the voltage gain, we must maximize the (small-signal)
load impedance.
Can we use an open circuit as load?
This is because the circuit still needs a path from VDD to ground for the
bias current of M1. 37
Example 3.4 It is possible to use the bulk (back gate) of a MOSFET as
the terminal controlling the channel. Shown in Fig. 3.9 is an example.
Determine the voltage gain if λ = 0.
From the small-signal MOS model developed in Chapter 2, we recall
that the drain current is given by gmbVin. Thus, Av = −gmbRD.

38
CS Stage with Diode-Connected Load
The transistor is always in saturation?
The drain and the gate have the same potential.

39
Interestingly, the impedance seen at the source of M1 is lower when
body effect is included. Why?
From a large-signal point of view, a diode-connected device acts as a
“square-root” operator if its current is considered the input and its VGS
or VGS − VTH the output (why?).
We return to this point later.

40
Example 3.5
Consider the circuit shown in Fig. 3.12(a). In some cases, we are
interested in the impedance seen looking into the source, RX .
Determine RX if λ = 0.

We sometimes say, “looking into the source of a

MOSFET, we see 1/gm”
41
We now study a common-source stage with a diode-connected load.

If the variation of η with the output voltage is neglected

The gain is independent of the bias currents and voltages (so long as
M1 stays in saturation). Input-output characteristic is relatively linear.

42
The linear behavior of the circuit can also be confirmed by large-signal
analysis.
Neglecting channel-length modulation for simplicity

Thus, if the variation of VTH2 with Vout is small, the

circuit exhibits a linear input-output characteristic.

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