Scribd
Upload
41 views14 pages

VHDL

This document discusses VHDL and its features. It begins with an introduction to VHDL, establishing it as a hardware description language standardized in 1987. It then describes VHDL's salient features such as being concurrent, supporting time as a parameter, and being technology and process independent. The next sections cover VHDL's different levels of abstraction, design units like entities and architectures, and data types. It concludes with examples of behavioral, dataflow, and structural modeling in VHDL.

Uploaded by

mcb
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
41 views14 pages

VHDL

This document discusses VHDL and its features. It begins with an introduction to VHDL, establishing it as a hardware description language standardized in 1987. It then describes VHDL's salient features such as being concurrent, supporting time as a parameter, and being technology and process independent. The next sections cover VHDL's different levels of abstraction, design units like entities and architectures, and data types. It concludes with examples of behavioral, dataflow, and structural modeling in VHDL.

Uploaded by

mcb
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 14

Introduction to VHDL

• Very high speed integrated circuit (VHSIC) Hardware Description


Language
• VHDL is a product of the VHSIC program funded by department of defence
USA
•VHDL was establishes as a IEEE 1076 standard in 1987
Salient Features of VHDL
•Concurrent
•Supports time as a parameter
•Highly typed lenguage
•Technology and process independent
•Permits operator overloading
•Permits better documentation
Performance specifications
Behaviour Test benches
Sequential descriptions
State machines
Dataflow Register transfers Level of
Selected assignments abstraction
Arithmetic operations
Boolean equations
Structure Hierarchy
Physical information
Design Units
• Entity declaration
• Package declaration
• Configuration declaration
• Architecture body declaration
• Package body declaration
Entity declaration : An entity declaration describes the
interface of a design entity through which it communicates
with other design entities in the same environment
Architecture body : Defines the functional composition of a
design (i.e) defines what the circuit actually does
Configuration declaration : Primary design unit used to
bind entity statements to particular architecture bodies to
form components of a design
Package declaration : used to collect commonly used
declarations for use globally among design units.
Package body : Contains the subprogram bodies of functions
and procedures declared in the package declaration.
ENTITY

Entity declaration
Interface declaration

Architecture body
Functional definition
ENTITY declaration is analogous to symbol of a component
entity nand2 is
A
port ( A,B : in bit ;
C: out bit ) ; nand 2 C
B
end nand2;
entity fulladder is
A
port ( A,B,Cin : in bit ; Sum
B fulladder
sum : out bit; Carry
Cin
carry : out bit ) ;
end fulladder;
Thus, entity declaration of a device tells us about
-Ports and their types
-Type of data they can hold i.e bit, bit_vector etc.
Port : in , out, inout, buffer
Architecture
• Schematic in conventional design methodology defines
functionality of design
• Architecture gives the functional behavior of the entity i.e.
how its inputs and outputs are related
• Architectures can be modeled in four different ways
Behavioral modeling Structural modeling
Data flow modeling Mixed modeling
Example :
architecture arch1 of nand2 is
begin
C <= A nand B;
end arch1;
Data Type
• Scalar types: enumeration, integer, physical,
floating point.
• Composite types: array, record, access.
Data Objects
• Constant
• Variable
• Signal
• file
begin
begin

Statement Statement
Statement
Statement
Statement
Statement
end
end

Concurrent Sequential
Concurrent statements Sequential statements

• Block statement • Wait statements


• Process statement • Variable assignment
• Assertion statement • Signal assignment
• Signal assignment • If statement
statement • Case statement
• Procedure calls • Loops
• Component instantiations • Next statement
• Null statement
• Procedure call
• Assertion statement
Example: Half adder
entity halfadder is
port ( X,Y : in bit ;
Sum, Carry: out bit ) ;
end nand2;
Data flow architecture
architecture dataflow of halfadder is
begin
sum <= ( not (X) and Y ) or ( X and not (Y) );
carry <= X and Y;
end dataflow;
Behavioral modeling
architecture behav of halfadder is
begin
process (X, Y)
begin
if X =‘0’ and Y =‘0’ then
sum<= ‘0’;
carry <= ‘0’;
elseif X =‘0’ and Y =‘1’ then
sum<= ‘1’;
carry <= ‘0’; continued….
elseif X =‘1’ and Y =‘0’ then
sum<= ‘1’;
carry <= ‘0’;
else X =‘1’ and Y =‘1’ then
sum<= ‘0’ ;
carry <= ‘1’;
end if;
end process;
end behav;
architecture structural of halfadder is
signal xbar, ybar, i ,j : bit;
component and
port ( A, B : in bit;
C : out bit ) ;
end and ;
component or
port ( E , F : in bit;
G : out bit ) ;
end or ;
component not
port ( A1 : in bit ; B1 : out bit ) ;
end not ; continued ……
begin
C0: not portmap ( X,xbar);
C5: not portmap ( Y,ybar);
C1: and portmap ( X,ybar,i );
C2: and portmap ( xbar,Y,j);
C3: or portmap ( i,j,sum);
C4: and portmap ( X,Y,carry);
end structural;

You might also like