Generation of Computers

First generation:
First computers were manufactured around 1946. Vacuum tubes were used to
build the various circuits required. Those computers were slow, generated lot of
heat & required large space.
Second generation:
Second generation computers used transistor as the basic switching element in
early 1950s. It improved speed, reduced power dissipation & required less space.
Third generation
Third generation computers used Integrated circuits(ICs). Each IC had hundreds of
transistors. It was in early 1960s & up to mid 1970s.
Fourth generation
IC technology further improved & LSI(Large scale Integrated circuit) was
introduced during 1970s. LSIs had thousands of transistors in it. This technology
introduced Microprocessors & Microcontrollers.
Fifth generation
These computers use VLSIs(Very Large Scale Integrated circuits) which contain
lakhs of transistors in a single chip.
 Classification of Computers

The digital computers are classified based on speed, storage capacity & word length

Microcomputer: These computers have a word length of 8 to 16 bits. They are slow
& have less data storage capacity. These are used for dedicated applications.

Minicomputer: These computers have a word length of 32 bits. The speed & data
storage capacity is moderate. These are used general purpose systems in the field
of data processing, process control & industrial applications.

Mainframe Compute: These computers have a word length of 64 bits. The speed is
very high & data storage capacity is very large. These are used for scientific
applications, business data processing & military applications.

Super computer: These computers have a word length of 64 bits. The speed is
higher than main frame computers. They use artificial intelligence. Objects are used
as input/output.
 Computer
The computer basically consists of three functional units namely CPU-Central
Processing Unit(uP), memory unit & input/output units.
“The Microprocessor is defined as the central processing unit of the
Microcomputer”
Memory
Unit

Input Output
Unit CPU Unit

Each of the units performs special functions. The heart of the computer is CPU. It
executes instructions & processes the data. The input & output units are the
means by which CPU communicates with the external world. The examples are
Keyboard, Mouse, Video display terminal & Printers.
 The memory unit is used to store the information. It usually consists of RAM
(Random Access Memory) & ROM (Read Only Memory). These are called
primary memories. It may also have floppy disks, magnetic hard disks &
optical disks. These are secondary memories & used for long term storage.

Memory Memory
Unit Unit

Input Output Input Output

Unit uP Unit Unit CPU Unit
 Difference between FD and HD
• Floppy disk is a small plastic storage device typically
capable of no more than 1.44Megabytes or storage. It
is also now rather out-dated thanks to advancements
in today's technologies. Generally floppy disks are
capable of reaching 250-300 bit/s read/write speeds.
• A hard disk is a mechanical drive with multiple disks
capable of storing 8Terabytes if not more worth of
data. Disk drives are capable of reaching read write
speeds of 300MB/s.Read more on Brainly.in -
https://brainly.in/question/4070684#readmore
 Features of 8086

1. The 8086 is a 16-bit processor. It means ALU, its internal registers & most of
its instructions are designed to work with 16-bit data.
2. The 8086 has a 16-bit data bus.
3. The 8086 has a 20-bit address bus so it can have a maximum of 1MB of
memory. It has 16-bit I/O address so it can access up to 64K I/O ports.
4. The data bus and 16-bit lower order address bus is multiplexed.
5. The 8086 has Fourteen 16-bit registers.
6. The 8086 requires a clock with 33% duty cycle for its internal timing. Its clock
speed is 5MHz, 8MHz or 10MHz.
7. The 8086 has a powerful instruction set with a range of addressing modes. It
can perform bit , byte , word & block operations.
8. The 8086 has two mode of operations Minimum & Maximum. In minimum
mode it works as a single microprocessor. Where as in maximum mode it
work in Multiprocessor configuration.
8086 ARCHITECTURE
 The block diagram consists of two internally divided separate functional
units. These are BUS INTERFACE UNIT (BIU) & EXECUTION UNIT (EU). They work
simultaneously. The division of work between these units speeds up the
processing.
BUS INTERFACE UNIT (BIU) :
The BIU provides the interface to external world. It generates the 20-bit
physical address & handles all the data transfers.
1. It fetches instruction from memory.
2. It reads / writes data from memory / ports.
3. It sends the addresses to memory / ports.
4. It supports an Instruction QUEUE.

QUEUE: The BIU fetches up to six instructions bytes belonging to next instructions.
These bytes are stored in FIFO - First In First Out register set called as QUEUE.
Fetching of the next instructions & execution of the current instruction is done
simultaneously .And this QUEUE makes use of pipelining & speeds up processing.
EXECUTION UNIT:
The EU is responsible for the instruction execution & has a control circuit to direct
its internal operations.
1. It picks up the instructions from the Queue of BIU.
2. It decodes the instructions & decides upon the various operations it has to
carry out. It then executes these operations.
3. It uses ALU to perform 16-bit Arithmetic & logical operations like ADD,
SUBTRACT, AND, OR, XOR, INCREMENT, DECREMENT, COMPLEMENT & SHIFT.
4. It updates the status of FLAG register (PSW Register).
5. It performs BIU from where the next instruction or data has to be read.
Register Organization of 8086
The 8086 contains Fourteen 16-bit registers. They are of different types.
1. General purpose registers: AX , BX , CX , DX.
2. Segment registers: CS , DS , SS , ES .
3. Index registers: SI , DI.
4. Pointer registers: SP , BP , IP.
5. Flag or Program status register.

General purpose registers: (AX , BX , CX , DX)

16-bit register High order 8-bit Low order 8-bit

Register Register
AX AH AL
BX BH BL
CX CH CL
DX DH DL
The general purpose registers are used for temporary storage of data &
intermediate results.
AX: The register AX is called as Accumulator. During multiplication 8-Bit x 8-Bit one
of the operand should be in AL and the result will store in AX (AH+AL). In case
of 16-Bit x 16-Bit the result will store in DX:AX. In case of Division by 8-Bit the
Quotient will be in AL & Remainder in AH , where as in case of 16-Bit Division
the Quotient will be in AX & Remainder in DX.
BX: It is used as a Base register. It contains the offset address of the memory
location in some addressing modes.
CX: It is used as an implicit counter in loop & string instructions. The register CL is
used as 8-bit counter in shift & rotate instructions.
DX: It is used to hold the 16-bit I/O address in I/O instructions.
Segment registers: (CS , DS , SS , ES)

FFFFF

64KB Extra Segment

64KB Stack Segment

64KB Data segment

64KB Code Segment

00000
FFFFF = 1111 1111 1111 1111 1111
00000 = 0000 0000 0000 0000 0000
Index registers: (SI , DI)
There are two index registers Source Index (SI) & Destination Index (DI). They acts
as general purpose registers also during string instructions.

Pointer registers: (SP , BP , IP)

There are three pointer registers. They are Instruction pointer (IP), Stack
pointer(SP) & Base pointer (BP). They are associated with Code segment & stack
segment.
1. The IP register keeps the track of 16-bit offset address of the next instruction
to be executed.
2. The SP register points the top of the stack.
3. The BP register is used as general purpose as well bottom of the stack.
Flag (or) Program status register

Six are status Flags: OF , SF , ZF , AF , PF , CF.

Three are control flags: DF , IF , TF
1. Carry Flag(CF): It is set if there is a carry out of the most significant bit
position resulting from an addition or if a borrow is needed at MSB during
subtraction. If no carry out or borrow is needed , the carry flag is reset.
2. Parity Flag(PF): if the lower order 8-bits of the result of an operation contains
odd number of 1’s then this bit set to “1”. If the lower order 8-bits contains
even number of 1’s then this bit remains to be “0”.
3. Auxiliary carry flag(AF): It is set to 1 if there is a carry out of bit 3 to bit 4
resulting from an addition or borrow is required from bit 4 to bit 3 for
subtraction.
4. Zero flag(ZF): It is set to “1” if the result of an arithmetic or logic operation is
zero. In case of non-zero it remains to be “0”.
5. Sign flag(SF): It is set to “1” if the MSB of the result is 1. it is set to “0”, if the
MSB of the result is zero during any operation. This flag is used with signed
numbers.
6. Overflow flag(OF): In case of a signed arithmetic operation, the overflow flag
is set to “1”, if the result is too large to fit in the number of bits available to
accommodate it. The overflow flag has no significance in unsigned arithmetic
operation.
7. Trap or Trace Flag(TF): It is used for single step control. It allows user to execute
one instruction of a program at a time for debugging. When TF=1, a program can
be run in single-step mode. The TF flag is restored to the state in which was
before the interrupt occurred.
8. Interrupt flag(IF): It is an interrupt Enable/Disable flag. If it is set to “1” interrupt
is enabled, if it is reset to “0 “ then the interrupt is disabled.
9. Directional Flag(DF): It is used during string operations. If it is set to “1” string
bytes are accesses from higher memory address to lower memory address.
When it is “0” the string bytes are accesses from lower address to higher
address.
Default Segment & Offset Registers

Default Segment Offset Memory operation

CS IP Instruction fetch
SS SP,BP or effective address Stack operation
Using BP as one of the register
DS BX/SI/DI or effective address using General data access
above registers
DS SI Source string data access
ES DI Destination string data
access
Generating 20-bit Physical address
Advantages of Memory Segmentation

1. It allows the memory capacity to be 1MB even though the actual addresses to
be handled by instructions are 16-bits
2. It allows use of separate memory areas for program, data & stack, thus the
protection of these is possible.
3. For large programs , it can use multiple segments for program code, Data &
Stack.
4. Program relocation can be very easily done.
 Physical Memory organization

FFFFFH FFFFEH
FFFFDH FFFFCH

512KB 512KB

00003H 00002H
[

00001H 00000H

Higher bank( Odd Bank) Lower bank( Even Bank)

BHE A0 Type of data transfer and bank selection

0 0 16-bit data transfer, both banks selected
0 1 8-bit data transfer, odd bank selected
1 0 8-bit data transfer , even bank selected
1 1 No data transfer , both banks disabled
8086 Pin Diagram
The pins & signals of 8086 can be classified as into five groups, they are as follows:
1. Address / Data bus
2. Address / status bus
3. Control & status signals
4. Interrupts & externally initiated signals.
5. Power supply & clock frequency signals.

1. Address / Data bus [AD0-AD15 (input/Output): Pins 16 to 2 & 39]

These signals are bi-directional & time multiplexed. If a bus carries
different types of signals at different times then it is called time multiplexed.
During the first clock cycle, during ALE, they contain address information (A0 to
A15) & in the remaining clock cycles they contain data (D0 to D15). During hold
acknowledge they will be in high impedance state.
2. Address / status bus [A16/S3-A19/S6(Output/Tristate): Pins 38 to 35]
These signals are output & time multiplexed. During the first clock cycle,
during ALE, they contain address information (A16-A19). In the remaining clock
cycles they contain status information(S3-S6). During HOLD acknowledge they will
be high impedance a state.
S3 S4 S5 S6 Signals are as below:
S3 & S4 indicate which segment register is being used for generating 20-bit
physical address
S3 S4 Segment Register
0 0 ES
0 1 SS
1 0 CS
(None in the case of I/O port access)
1 1 DS
S5 indicates the current status (0 or 1) of interrupt flag.
S6 is always “0” and is not used.

3. Control & Status Signals

1. RD: Read [output/tri state]: pin 32
A low on this signal indicates read operation from memory or I/O. during HOLD
acknowledge it will be in high impedance state.
2. BHE/S7: Bus High Enable/S7 9output): pin 34
It is an output & time multiplexed. During the first clock cycle it contains BHE. In
the remaining cycles it contains S7.
BHE is active low signal. When low it enables the MSB data bus (D8-D15) during
read/ write operation.
S7 is always High.
4. Interrupts & externally initiated signals
1. NMI: Non mask able interrupt(input): Pin 17
This is a non mask able interrupt request to CPU from external devices. It is a
positive edge triggered signal. It cannot be disabled using interrupt flag.
2. INTR: Interrupt (Input): Pin 18
It is a mask able interrupt request to CPU from external devices. It is a level
triggered signal. It can be enabled or disabled using interrupt flag. To enable set
the interrupt flag.
3. RESET: Reset (input): Pin 21
This is a input signal which resets the uP. This should be held high for at least 4
clock cycles.
4. READY: Ready (input): Pin 22
This input signal indicates to the CPU whether memory or I/O device is ready for
data transfer. If it is High then they are ready. If it is Low then CPU waits for it to
become High.
5. TEST: test (input): Pin 23
This input signal is used to synchronize external hardware. It is tested by WAIT
instruction. If it is high, WAIT instruction waits for it to become low. If it is low
WAIT instruction will be NOP. It is normally connected to 8087 coprocessor.
6. MN/MX: Minimum / Maximum (input) : Pin 33
This signal selects the minimum or maximum mode operation of the uP. If it is low
it works in maximum mode and if it is high works in minimum mode.

5. Power supply & clock frequency signals.

1. GND: Ground (input) : Pin 1 & 20
This input should be connected to the negative terminal of the DC power supply.
2. CLK: clock (input): Pin 19
This input clock signal provides the basic timing for the uP with 33% duty cycle.
3. Vcc : power Supply (input) : Pin 40
This input is connected to the positive terminal of +5V DC power supply.
Minimum Mode Configuration of 8086
There are 8 signals which are used in minimum mode of 8086. the 8 signals
generated by minimum mode belong to control, status, interrupt & externally
initiated function. They are as follows:
1. ALE : Address Latch Enable (output): Pin 25
This signal is used to latch the addresses & BHE signal. This way A0-A15gets
separated from D0-D15,A16-A19 gets separated from S3-S6 & BHE gets separated
from S7.
2. DEN : Data Enable (output): Pin 26
This signal is used to activate the data transceivers. It is an active low signal. When
high data transceivers will be in high impedance state.
3. DT/ R : Data Transmit/Receive (output): Pin 27
This signal is used to control the direction of data bus on data transceivers. When
it is high data is transmitted from CPU and when low data is received by CPU.
4. M / IO : Memory / Input-Output (Output/tri state): Pin 28
This signal selects memory or I/O Operation. When high memory & when low
then I/O is selected. This will remain High impedance during hold acknowledge.
5. WR : Write ( Output/ tri state): Pin 30
A low on this signal indicates that data on the data bus is valid & can be written
into memory or I/O. during hold acknowledge it will remain in high impedance
state.
6. INTA : Interrupt Acknowledge (Output) : Pin 24
This signal is activated by CPU in response to INTR signal. This signal is actually
acknowledging the interrupt received on INTR. It is used by the interrupting
device to send interrupt type number to the CPU.
7. HLDA : Hold Acknowledge(Output): Pin 30
This signal will be made high by CPU to indicate that hold request has been
accepted & CPU relinquishes the buses so that they can be used by requesting
device.
8. HOLD : Hold (Input) : Pin 31
This input indicates a request for the bus by I/O devices or DMA controller. If it is
high , uP stops executing instructions, & puts its buses into high impedance.
Maximum Mode Configuration of 8086
There are 8 signals which are used by maximum mode of 8086. these signals are
related to status instruction queue & multiprocessor configuration control. These
are described as below:
1. QS1,QS0 : Queue Status (Output) : Pin 24 & 25
These signals indicate the status of instruction queue during the previous clock
cycle. These are accessed by the coprocessor 8087.
QS1 QS0 Function
0 0 Queue is idle
0 1 First byte of op code
1 0 Queue is empty
1 1 Subsequent byte of op code

2. S0 , S1 , S2 : status bits (output) : Pin 26, 27 & 28

These signals indicate the status of current bus cycle i.e., type of machine cycle. In
a machine cycle a specific type of activity takes place. These signals are decoded
by bus controller.
 S2 S1 S0 Machine Cycle

0 0 0 Interrupt acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Instruction (Op-Code) Fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive (Inactive)

3. LOCK: Lock (output) : Pin 29

This signal indicates that an instruction with lock prefix is being executed & system
bus cannot be used by other processors or controllers. This signal is useful in multi
processor configuration where system bus is shared. CPU can give the bus to other
processors on request, during execution of an instruction also. But lock prefix to
instruction ensures that system bus is released only after completion of the
instruction.
4. RQ1 / GT1 , RQ0 / GT0 : Request / Grant (Input output) : Pin 30 & 31
These signals are used as inputs & outputs. Other processors send the request for
the system bus(input) & 8086 uP sends the Grant for that request, using these
signals. Both signals are similar hence two requests can be given simultaneously. ,
RQ0 / GT0 has the higher priority.
Minimum mode configuration
In this mode MN/MX is connected to +5V. 8284 is a clock generator. It provides
three output signals CLK , Ready & Reset which are connected to CPU. CLK signal is
derived from the basic clock of crystal connected to 8284. RDY and RESET signals
are synchronized by 8284 & given as inputs to CPU. Wait state generator controls
RDY signal. RESET signal becomes active on power up or on pressing the reset
switch. The 74LS244 is a unidirectional buffer for control signals. The three latches
74373/8282 are used to de-multiplex address A0-A19 & BHE from AD0-AD15,
A16/S3-A19/S6 & BHE/S7. The two 74245/8286 transceivers are bidirectional
buffers for data bus.
Maximum mode configuration
In this mode MN/MX is connected to ground. All the blocks are same as minimum
mode except 8288 bus controller. This controller generates various control
signals. CLK, S0, S1, S2 are the inputs to 8288. the output signals from 8288 are
DEN, DT/R, ALE, MRDC, MWTC, AMWC, IORC, IOWC, AIOWC & INTA. Out of
these signals DEN, DT/R, ALE & INTA signals are same as generated by CPU in
minimum configuration. MRDC & MWTC are for memory read & write
operations. AMWC is for advanced memory write. IORC & IOWC are for I/O read
& write operations. AIOWC is for advanced I/O write
Timing Diagram