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Power

Power planning involves forming power rings around cores and macros, creating power straps to tap power from rings to the core area, and running standard cell rails to distribute power to cell pins. It aims to supply uniform power within IR drop limits by managing power dissipation and temperature increases. Key steps include placing I/Os, macros, and power pads, and running power structures like rings, stripes, and rails to distribute power while preventing electromigration and IR drop issues.

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378 views18 pages

Power

Power planning involves forming power rings around cores and macros, creating power straps to tap power from rings to the core area, and running standard cell rails to distribute power to cell pins. It aims to supply uniform power within IR drop limits by managing power dissipation and temperature increases. Key steps include placing I/Os, macros, and power pads, and running power structures like rings, stripes, and rails to distribute power while preventing electromigration and IR drop issues.

Uploaded by

veeru
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Power planning:

 Power planning is done to provide uniform supply


voltage to all cells in the design.
 Power Planning is one of the most important stage in
Physical design.
 Power planning is used to provide power to macros
and standard cells with in the given IR-Drop limit.
Inputs for Power planning:
 Data base with floor plan information.
 library file, lef file.
 Power dissipation: Increase in temperature inside the device.
 Temperature Increase: Will effect proper operation and
reliability.
Power planning is done by core cell power management:
 VDD and VSS rings are formed around the core and macros.
 Power straps are created in the core area to tap power from core
rings.
 Standard cell rails are created to tap power straps to
std cell power/ground pins.
Make sure all the I/O ports are placed and fixed.
Make sure all the macros are placed and fixed.

 Power planning Targets:-


 To supply uniform power to all the cells.
 To reduce IR drop.
 To reduce electromigration

.
In power planning the power follows can be
Power pads

Power rings

Power stripes Macros

Follow pins

Standard cell
 Generally the follow pins are created by the
lower metals and they are connected with
power stripes with special vias are called
stack vias.
 Stack via:-Group of vias placing in a stack
manner
 Rings:
• VDD & VSS are formed around the core and Macro.
 Strips:
• Carries VDD & VSS around the chip
• Carries VDD & VSS from rings across the chip
• Power stripes are created in the core area to tap power from core rings to the core
area.
 Rails:
• Connect VDD & VSS to the standard cell
• Standard cell rails are created to tap power from power strips to standard cell
power/ground pins.
 Trunks:
• Connects power pads to power rings.
 Block level
 To carry power around the periphery of a die and
standard cells core area.
 Rings are put in higher level routing layers(Low
resistance metal layers).

Macro power ring Core power ring


 I/O & Power pad placement.
 Pad ring creation.
 Typical power structure.
 Types of bumps.
 Bumps and How to route them.
 Full chip level:
 Voltage transfer in metal a drop occurs due to resistance of metal this is known
as IR drop.
 The causes for IR Drop are
 The standard cells are far away from power stripes
 Cell density (If more cells are present in the one region )
 High drive strength
 Via missing

IR drops are two types:-


1. S t a t i c I R d r o p
2.Dynamic P o w e r D r o p
Static IR drop:-
 Independent of the cell switching the drop is calculated with the
help of wire resistance.
 Methods to Improve static IR drop
. Increase the width of wire
 Dynamic IR drop:IR drop is calculated with the help of the switching
of the cells.
 We can improve dynamic IR drop by below method

. Placing decap cells in between them


Decap cells:
 These are the temporary capacitors which are added in the design
between power and ground rails to counter the functional failure due to
Dynamic IR drop.
 3% to 8% of the core physical area is required for decap cells.
Advantages:
 To decrease noise effect(Dynamic IR drop) &
current spikes.
 To reduce glitches and ground bounds.
Disadvantages:
 These cells offers more delay and if we use
more decaps that results more power
dissipation
 Electromigration (EM) is the movement of material that results from
the transfer of momentum between electrons and metal atoms
under influence of an applied electric field.
 This momentum transfer causes the metal atoms to be displaced
from their original positions so that opens and shorts will happens.

Remedies for avoiding of electromigration:

 Increasing width of the metal.


 Spacing between the metals by using NDR’S rules(double width,
double spacing)
 P O W E R - > P O W E R PLANNING->ADDSTRIPES
Go to Power->Power Planning->Add Stripes and fill out the form as follow.
 Connect_pg_net:-Create logic power and
ground leaf cells.
 Automatic:-
 Icc2_shell>connect_pg_net –automatic
 Mannual:-
 Icc2_shell>connect_pg_net –net VDD
 Icc2_shell>connect_pg_net –net VSS

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