Architecture of 8085

Block Diagram of 8085

The internal architecture of 8085
Includes

 Arithmetic and Logical Unit

 Register Array
 Instruction Register and Decoder
 Interrupt Control
 Serial I/O Control
 Timing and Control Unit
 Internal Data Bus
Units of 8085

1. Processing Unit
2. Storage and Interface Unit
3. Instruction Unit
4. Interrupt and Serial input/output unit
1. Processing Unit

 ALU

 Accumulator

 Temporary Register

 Flags
ALU
 The ALU performs the actual numerical and logic operation such as ‘add’,
‘subtract’, ‘AND’, ‘OR’ etc.
 Uses data from memory and from Accumulator to perform arithmetic
operation and always stores result of operation in Accumulator.
 The sequence of operations in ALU are given below
 One operand is in the A register
 The other may be in one of the GPR or memory location, which will be transferred to the
temporary register(TR)
 The contents of A and TR are the inputs of ALU on which specified operation is performed
 The result of ALU operation is transferred in the A register through internal data bus
 The content of the flag register will be changed depending on the result
Accumulator

 The accumulator is an 8-bit register that is a part of processing unit.

 This register is used to store 8-bit data and to perform arithmetic and logical
operations. The result of an operation is stored in the accumulator.
 The accumulator is also identified as register A.
Flag register

 8085 has 8-bit flag register. There are only 5 active flags.
 Flags are flip-flops which are used to indicate the status of the accumulator and
other register after the completion of operation.
 These flip-flops are set or reset according to the data condition of the result in the
accumulator and other registers.
2. Storage and Interface Unit
 General Purpose Registers
 Stack Pointer
 Program Counter
 Increment/Decrement Address Latch
 Address Buffer
 Address/Data Buffer
General Purpose Registers

 There are six 8-bit general purpose registers B, C, D, E, H & L.

 General purpose registers are used for temporary storage of data and
intermediate results while the processor is executing the program.
 Two eight bit registers can be combined for handling 16-bit data and
Combination of two 8-bit registers is known as pair.
 Valid register pairs are B-C, D-E, H-L.
 The H-L pair is used to address memories.
Stack pointer

 The stack pointer is a 16-bit register which basically serves two purposes.

a) Points towards the stack memory. Initially it indicates the beginning of the
stack memory. Whenever something is added to the stack, the stack pointer is
decremented and whenever something is removed from the stack the stack
pointer is incremented. Hence the stack pointer always points to the top of the
stack.
b) Stack pointer also points towards the memory location where the µP has to go
after attending an interrupt or a subroutine; therefore it acts as a bookmark.
Program Counter

 It is a 16-bit register which holds the address of the instructions.

 Initially it indicates towards the starting address of the program but after the
first instruction is fetched the program counter automatically gets incremented
by one and points towards the next instruction.

 This process continues till the end of the program.

Increment/Decrement address latch

 It is another 16-bit internal register latch available in the register section for
internal operations and is not accessible to the user.
 It selects an address to be sent out from the program counter, from the stack
pointer, or from one of the 16-bit register pairs.
 It latches this address onto the address lines for the required time.
 This 16-bit circuit is used to increment or decrement the contents of program
counter or stack pointer as a part of execution of instructions related to them
Address /Data buffer and Address buffer

 Address/Data Bus Buffer (AD0 to AD7) is a 8-bit bidirectional buffer.

 Address Bus buffer( A8 to A15) is a 8-bit unidirectional buffer.
 The contents of the stack pointer and program counter are loaded into the address buffer and
address-data buffer.
 These buffers are then used to drive the external address bus and address-data bus.
 As the memory and I/O chips are connected to these buses, the CPU can exchange desired data to
the memory and I/O chips
 The address-data buffer is not only connected to the external data bus but also to the internal data
bus which consists of 8-bits.
 The address data buffer can both send and receive data from internal data bus
3. Instruction Unit
 Instruction Register
 Instruction Decoder
 Timing and Control Section
Instruction Register and Decoder
 The first word of an instruction is the operation code, i.e., binary code for that
instruction.
 In the first machine cycle of any instruction µ𝑝 fetches the instruction from the
memory.
 The op-code representing the instruction to be executed is fetched from the
(program) memory location pointed to by (PC) and loaded into the instruction
register (IR).
 The IR passes this op-code to the instruction decoder which interprets this op-
code appropriately in order to decide what operation needs to be done for
executing this instruction.
 The instruction decoder tells the control unit the type of instruction to be
executed; the number of machine cycles necessary to execute the instruction
etc.
Contd.

 E.g. if the instruction is ADI 04H, then the first binary code read by the µ𝑝 is C6H into
the (IR).
 After decoding this, the decoder will recognize that another memory read cycle is
required to read 04H to be added to the number in the accumulator.
 The decoder will direct the control circuit to send out another memory read pulse
and transfers the data coming on the data bus into the temporary register (Temp),
so that it can be added to the accumulator.
 When the addition is completed the control circuit directs the result back to the
accumulator.
 The program counter is then incremented to point the next memory address and
send out another memory read pulse to read the µ𝑝 code of next instruction from
memory.
Timing and Control Section
Contd.
 Timing and control unit is a very important unit as it synchronizes the registers and flow
of data through various registers and other units.
 It provides timing & control signals necessary to all the operations in the
microcomputer.
 This unit consists of an oscillator and controller sequencer which sends control signals
needed for controls the flow of data between the microprocessor and peripherals
(input, output & memory).
 The oscillator generates two-phase clock signals which aids in synchronizing all the
registers of 8085 microprocessor.
Signals that are associated with
Timing and control unit are:
1. Control Signals: READY, RD(active low), WR (active low), ALE

2. Status Signals: S0, S1, IO/M(active low)

3. DMA Signals: HOLD, HLDA

4. RESET Signals: RESET IN(active low), RESET OUT

What is Clock ?

 We need some timing or clocking mechanism so as to decide when the output is

going to change i.e. at which point of time things will change.
 A clock signal is nothing but a train of pulses that oscillates between a high and a
low state that is, which alternates between 0 and 1 values.

A clock generator is used to generate a clock, which is an oscillator that provides a square
wave output.
Clock cycle
 The speed of a computer processor, or CPU, is determined by the clock
cycle, which is the amount of time between two pulses of an oscillator.
 The higher number of pulses per second, the faster the computer
processor will be able to process information.
 The frequency of a processor is measured in clock cycles per second
4. Interrupt Control Unit
 Interrupts are the Signals generated by external devices to request the
microprocessor to perform a task. So it’s a mechanism by which an I/O device or
an instruction can suspend the normal execution of processor and get itself
serviced.
 Consider that a microprocessor is executing the main program. Now whenever the
interrupt signal is enabled or requested the microprocessor shifts the control from
main program to process the incoming request and after the completion of
request, the control goes back to the main program.
 On occurring of interrupt the microprocessor temporarily stops the execution of
main program and transfers control to specific special routine known as "Interrupt
Service Routine"(ISR). After ISR control is transferred back to main program.
 Interrupt signals present in 8085 are Trap, RST 7.5, RST 6.5, RST 5.5, INTR.
Serial I/O control section

 Serial I/O is a method of communicating data between devices,

typically a computer and its peripherals, in which the individual data
bits being sent and receive sequentially.
 The microprocessor performs serial data input or output (one bit at a
time). In serial transmission, data bits are sent over a single line, one
bit at a time.
 The 8085 has two signals to implement the serial transmission: SID
(serial input data) and SOD (serial output data)
8085 System Bus
 System bus is basically a group of communication lines/wires that are
responsible for transferring information between different units of the
device or peripherals.
 A typical microprocessor communicates with memory and other
devices using three buses:
Address bus
Data bus and
Control bus.
Address bus:
 Address bus is a unidirectional group of 16 lines i.e. bits flow
in one direction from the µP to the peripheral devices.
 The 8085 µP with it’s 16 address lines is capable of
addressing 216=65536 (64K) memory locations.
 The address bus has 8 signal lines A8 – A15 which are
unidirectional , known as higher order address bus.
 Other 8 address bits are multiplexed (time shared) with the
8 data bits i.e. AD0 – AD7, known as lower order address
bus as well as data bus.
Contd.

 So, the bits AD0 – AD7 are bi-directional and serve as

A0 – A7 and D0 – D7 at the same time.
 During the execution of the instruction, these lines
carry the address bits during the early part, then
during the late parts of the execution, they carry the 8
data bits.
Data bus:

 Data bus carries data in binary form, between

microprocessor and peripheral devices as well as
memory.
 It is a group of bidirectional 8-bits from AD0 – AD7 .
 Data bus is time multiplexed with the lower order
address bus, i.e. AD0 – AD7
 They are used as low-order address bus as well as data
bus and therefore they are known as multiplexed
address/data bus.
Control bus:

 The control bus is combination of various single lines that

carry control signals.
 The control lines are not group of lines like address and
data bus but are individual lines.
Demultiplexing of AD7-AD0
 AD7– AD0 lines are serving a dual purpose and that they need to be
demultiplexed to get all the information.
 The high order bits of the address remain on the bus for three clock
periods. However, the low order bits remain for only one clock period
and they would be lost if they are not saved externally.
 To make sure we have the entire address for the full three clock
cycles, we will use an external latch to save the value of AD7– AD0
when it is carrying the address bits.
 We use the ALE signal to enable this latch
Contd.
Given that ALE operates as
a pulse during T1, we will be
able to latch the address.
Then when ALE goes low,
the address is saved and
the AD7– AD0 lines can be
used for their purpose as
the bi-directional data
lines.
Contd.

 The high order address is placed on the address bus and

hold for 3 clock periods.
 The low order address is lost after the first clock period, this
address needs to be hold however we need to use latch.
 The address AD7 – AD0 is connected as inputs to the latch
74LS373.
 The ALE signal is connected to the enable (G) pin of the
latch and the OC – Output control – of the latch is
grounded
Contd.
 In first T state Microprocessor generates the address on Address Bus, half
portion of address (lower order address) is generated on AD0-AD7 . This
Address bits are captured by D latches and stored in.
 During next cycles say T2, T3 and so on, MP can use AD0-AD7 as Data Bus to
send receives data. During this period the initially generated Address is also
available at output pins of D Latches.
 74LS373is used as Address Latch it contains 8 D Latches to store lower half of
address.(8 bits).