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Vlsi

This document discusses MOS technology, including nMOS and pMOS transistors, and their operation in different modes based on gate-source voltage. It also summarizes the basic processes used to fabricate nMOS transistors, including epitaxial growth, oxidation, photolithography, diffusion, and metalization. Finally, it provides overviews of CMOS technology, the different CMOS fabrication processes, and comparisons between CMOS and bipolar technologies.

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Arya Vijayan
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61 views56 pages

Vlsi

This document discusses MOS technology, including nMOS and pMOS transistors, and their operation in different modes based on gate-source voltage. It also summarizes the basic processes used to fabricate nMOS transistors, including epitaxial growth, oxidation, photolithography, diffusion, and metalization. Finally, it provides overviews of CMOS technology, the different CMOS fabrication processes, and comparisons between CMOS and bipolar technologies.

Uploaded by

Arya Vijayan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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MOS technology

ENHANCEMENT and DEPLETION type nMOS


pMOS
Enhancement mode nMOS
transistor action
Accumulation mode
Vgs<<Vt

Depletion mode
Vgs==Vt

Inversion mode
Vgs>>Vt
nMOS fabrication
nMOS fabrication
nMOS fabrication
nMOS fabrication
nMOS fabrication
Basic Planar processes
 Silicon wafer preparation
 Epitaxial growth
 Oxidation
 Photolithography
 Diffusion
 Ion implantation
 Isolation technique
 Metalization
 Assembly processing and packaging
Epitaxial Growth
 Deposition of a
layer on a substrate Ordered,
which matches the crystalline
growth;
crystalline order of NOT
the substrate epitaxial
 Homoepitaxy
 Growth of a layer of
the same material
as the substrate
Epitaxial
 Si on Si growth:
 Heteroepitaxy
 Growth of a layer of
a different material
than the substrate
 GaAs on Si
CMOS technology
CMOS technology
 Complementary metal–oxide–
semiconductor

 Uses complementary and symmetrical


pairs of p-type and n-type MOSFETs
for logic functions

 Low static power consumption


CMOS Fabrication
• P-Well process

• N-well process

• Twin-tub process

• Silicon-on-Insulator
CMOS p-Well Process
CMOS p-Well Process
CMOS p-Well Inverter
N-Well Process
Twin Tub process
 Starts with a substrate of high
resistivity n-type material
 Create both n-well and p-well regions
 Separate optimization of n and p
transistors
TWIN TUB inverter
Silicon on Insulator
BiCMOS Technology
npn transistor

npn transistor
BiCMOS Technology
 npn transistor is formed in an n-well
 Additional p+ base region is located
in the well to form p-base region
 Buried n+ sub collector(BCCD) to
reduce resistance of n-well collector
 Standard n-well process is extended
to include further masks to add the
two layers
Ids – Vds characteristics

nMOS transistor
(1)

(2)

(3)
(4)

(5)

(6)
 Voltage along the channel varies
linearly with distance x from the source
 Due to the IR drop in the channel
 Average value of this voltage in the
channel is Vds/2
 Effective gate voltage is
Vg = Vgs - Vt
Non-Saturated Region Vds < Vgs - Vt

Charge/unit area (7)

(8)

where

(9)

38
Non-Saturated Region Vds < Vgs - Vt

(10)

(11)

(11 a)

39
Non-Saturated Region Vds < Vgs - Vt

(11 b)

therefore

(11 c)

40
Non-Saturated Region Vds < Vgs - Vt

 Co -> gate capacitance per unit


area
therefore Cg = CoWL

(11 d)
Saturated Region Vds = Vgs - Vt

(12 a)

(12 b)

(12 c)

(12 d)

42
43
44
Threshold variations
Threshold Variations
 Drain Induced Barrier Lowering
 Punch Through
 Hot carrier effects
Source-Drain resistance

Modeling the series resistance


Source-Drain resistance
The resistance of the source(drain) region

Rc ->Contact resistance

->Sheet resistance per square of


the drain source diffusion

LS,D -> Length of the source or drain region


W -> Width of the transistor
Variations in I-V characteristics
1) Velocity Saturation 2) Mobility Degradation
Narrow width effect
CMOS technology Bipolar technology

 Low static power  High power dissipation


dissipation
 High i/p impedance  Low i/p impedance
 High packing density  Low packing density
 High noise margin  Low voltage swing
logic
 Low fan-out  High fan-out
 Low o/p drive current  High o/p drive current
 Low gm  High gm
 Bidirectional  Unidirectional
 A near ideal switching
device

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