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Verilog Switchlevel Programming: Programming Assignment 13 & 14: Switch-Level Modeling I

Write a Verilog module to implement a 16-to-1 multiplexer using switch-level modeling. You may use the tranif0 and tranif1 switches for the purpose, in addition to any other components.

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80 views

Verilog Switchlevel Programming: Programming Assignment 13 & 14: Switch-Level Modeling I

Write a Verilog module to implement a 16-to-1 multiplexer using switch-level modeling. You may use the tranif0 and tranif1 switches for the purpose, in addition to any other components.

Uploaded by

ramjidr
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Verilog Switchlevel Programming

Programming Assignment 13 & 14:


Switch-Level Modeling I
Write a Verilog module to implement a 16-to-1 multiplexer using switch-level
modeling. You may use the tranif0 and tranif1 switches for the purpose, in
addition to any other components.

module mux16to1 (F, A, SEL);


input [15:0] A;
input [3:0] SEL;
output F;
wire [0:15]t1,t2,t3;
tranif0 (A[0], t1[0], SEL[0]); tranif0 (t1[0], t2[0], SEL[1]);tranif0 (t2[0], t3[0], SEL[2]);tranif0 (t3[0], F, SEL[3]);
tranif1 (A[1], t1[1], SEL[0]); tranif0 (t1[1], t2[1], SEL[1]);tranif0 (t2[1], t3[1], SEL[2]);tranif0 (t3[1], F, SEL[3]);
tranif0 (A[2], t1[2], SEL[0]); tranif1 (t1[2], t2[2], SEL[1]);tranif0 (t2[2], t3[2], SEL[2]);tranif0 (t3[2], F, SEL[3]);
tranif1 (A[3], t1[3], SEL[0]); tranif1 (t1[3], t2[3], SEL[1]);tranif0 (t2[3], t3[3], SEL[2]);tranif0 (t3[3], F, SEL[3]);
tranif0 (A[4], t1[4], SEL[0]); tranif0 (t1[4], t2[4], SEL[1]);tranif1 (t2[4], t3[4], SEL[2]);tranif0 (t3[4], F, SEL[3]);
tranif1 (A[5], t1[5], SEL[0]); tranif0 (t1[5], t2[5], SEL[1]);tranif1 (t2[5], t3[5], SEL[2]);tranif0 (t3[5], F, SEL[3]);
tranif0 (A[6], t1[6], SEL[0]); tranif1 (t1[6], t2[6], SEL[1]);tranif1 (t2[6], t3[6], SEL[2]);tranif0 (t3[6], F, SEL[3]);
tranif1 (A[7], t1[7], SEL[0]); tranif1 (t1[7], t2[7], SEL[1]);tranif1 (t2[7], t3[7], SEL[2]);tranif0 (t3[7], F, SEL[3]);
tranif0 (A[8], t1[8], SEL[0]); tranif0 (t1[8], t2[8], SEL[1]);tranif0 (t2[8], t3[8], SEL[2]);tranif1 (t3[8], F, SEL[3]);
tranif1 (A[9], t1[9], SEL[0]); tranif0 (t1[9], t2[9], SEL[1]);tranif0 (t2[9], t3[9], SEL[2]);tranif1 (t3[9], F, SEL[3]);
tranif0 (A[10], t1[10], SEL[0]); tranif1 (t1[10], t2[10], SEL[1]);tranif0 (t2[10], t3[10], SEL[2]);tranif1 (t3[10], F, SEL[3]);
tranif1 (A[11], t1[11], SEL[0]); tranif1 (t1[11], t2[11], SEL[1]);tranif0 (t2[11], t3[11], SEL[2]);tranif1 (t3[11], F, SEL[3]);
tranif0 (A[12], t1[12], SEL[0]); tranif0 (t1[12], t2[12], SEL[1]);tranif1 (t2[12], t3[12], SEL[2]);tranif1 (t3[12], F, SEL[3]);
tranif1 (A[13], t1[13], SEL[0]); tranif0 (t1[13], t2[13], SEL[1]);tranif1 (t2[13], t3[13], SEL[2]);tranif1 (t3[13], F, SEL[3]);
tranif0 (A[14], t1[14], SEL[0]); tranif1 (t1[14], t2[14], SEL[1]);tranif1 (t2[14], t3[14], SEL[2]);tranif1 (t3[14], F, SEL[3]);
tranif1 (A[15], t1[15], SEL[0]); tranif1 (t1[15], t2[15], SEL[1]);tranif1 (t2[15], t3[15], SEL[2]);tranif1 (t3[15], F, SEL[3]);
endmodule
Write a Verilog module using switch-level modeling to
implement the function F = (A’.B + C,D)’ using CMOS logic. You
may use the nmos and pmos transistors for the purpose.
• module computeF (F, A, B, C, D);
• input A, B, C, D;
• output F;
• supply1 Vdd;
• supply0 Vss;
• wire abar,w1,w2,w3;
• pmos(abar, Vdd,A);
• nmos(abar,Vss,A);
•
• pmos (w1,Vdd,abar);

• pmos (w1,Vdd,B);
•
• pmos (F,w1,C);

• pmos (F,w1,D);
•
• nmos (F,w2,abar);

• nmos (w2,Vss,B);
• nmos (F,w3,C);

• nmos(w3,Vss,D);

• endmodule

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