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Sequential Logic Circuits

The document discusses synchronous sequential logic and latches. It describes how synchronous sequential circuits use clock signals to synchronize storage elements like latches and flip-flops. Latches can maintain a binary state and come in different types like SR latches, which can be constructed using NOR or NAND gates. SR latches have set, reset, and undefined states that depend on input signals. Control inputs can prevent undefined states. Problems can arise when latch state transitions occur within a single clock cycle.

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Mona Sayed
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17K views

Sequential Logic Circuits

The document discusses synchronous sequential logic and latches. It describes how synchronous sequential circuits use clock signals to synchronize storage elements like latches and flip-flops. Latches can maintain a binary state and come in different types like SR latches, which can be constructed using NOR or NAND gates. SR latches have set, reset, and undefined states that depend on input signals. Control inputs can prevent undefined states. Problems can arise when latch state transitions occur within a single clock cycle.

Uploaded by

Mona Sayed
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 18

UMST

ENG322 DIGITAL LOGIC DESIGN

LECTURE1
SYNCHRONOUS
SEQUENTIONAL LOGIC -
LATCHES

Kauther Mohammed Amer Mahdi


CONTENTS

 Sequential Circuits
 Storage Elements: Latches

 Storage Elements: Flip-Flops

 Analysis of Clocked Sequential Circuits

 State Reduction and Assignment

 Design Procedure

ENG322 DIGITAL LOGIC DESIGN October 1, 2019


2
SEQUENTIAL CIRCUITS

 The inputs and present state of the


storage elements determine the value of
the outputs.
 The next state of the storage elements is
also a function of external inputs and the
present state.
ENG322 DIGITAL LOGIC DESIGN October 1, 2019
3
TWO TYPES OF SEQUENTIAL CIRCUITS:

 Their classification depends on the timing of


their signals.

 Synchronous sequential circuit: its


behavior can be defined from the knowledge
of its signals at discrete instants of time.
 Asynchronous sequential circuit: its
behavior depends upon the input signals at
any instant of time and the order in which
the inputs change. Storage elements are used
as time-delay devices.
ENG322 DIGITAL LOGIC DESIGN October 1, 2019 4
SYNCHRONOUS CLOCKED SEQUENTIAL
CIRCUIT

A synchronous sequential circuit employs


signals that affect the storage elements
only at discrete instants of time.
 Synchronization is achieved by a clock
generator that provides periodic clock
pulses.
 Clock pulses are distributed throughout
the digital system in such a way the
storage elements are affected only with
the arrival of each pulse.
 Storage elements are called flip-flops.

ENG322 DIGITAL LOGIC DESIGN October 1, 2019 5


SYNCHRONOUS CLOCKED SEQUENTIAL
CIRCUIT

Synchronous Clocked Sequential Circuit

ENG322 DIGITAL LOGIC DESIGN October 1, 2019 6


STORAGE ELEMENTS: LATCHES

October 1, 2019
A flip-flop circuit can maintain a binary
state.

ENG322 DIGITAL LOGIC DESIGN


 There are different types of flip-flops.
 Basic type of flip-flops are Latches.
 Latches are basic circuits from which all
types of flip-flops are constructed.
 Latches are used more in asynchronous
sequential circuits. 7
SR LATCH

 The SR Latch is a circuit with two cross-coupled


NOR gates or two cross-coupled NAND gates, as
will be explained next.

ENG322 DIGITAL LOGIC DESIGN October 1, 2019 8


SR LATCH WITH NOR GATES

October 1, 2019
SR Latch has two useful states:

 Set state: when output Q=1 and Q’=0, and


 Reset state: when output Q=0 and Q’=1.

These states can be used to store 1-bit information.


Output Q and Q’ are normally complement of each
other.
 Undefined state: when Q=0 and Q’=0, occurs when
both inputs R and S are equal to 1 at the same time.
SR LATCH WITH NOR GATES
 Under normal conditions, both inputs of
the latch (R and S) remain at 0 unless the
state has to be changed.
 To let latch in the set state, S must be 1
 To let latch in the reset state, R must be 1
 The inputs S and R must go back to 0
before any other changes, to avoid the
occurrence of the undefined state.
 The latch goes to the set state or reset
state and stays there, even after both
inputs return to 0.
ENG322 DIGITAL LOGIC DESIGN October 1, 2019 10
SR LATCH WITH NOR GATES

 When both inputs Sand Rare equal to 0, the latch


can be in either the set or the reset state,
depending on which input was most recently a 1.
October 1, 2019 11
SR LATCH WITH NAND GATES

October 1, 2019
As before, the SR Latch has two useful states:
 Set state: when output Q=1 and Q’=0.

 Reset state: when output Q=0 and Q’=1.

EE345 - Introduction to Microcontrollers


Output Q and Q’ are normally complement of
each other.
 Undefined state: when Q=1 and Q’=1, occurs
when both inputs R and S are equal to 0 at the
same time.

12
SR LATCH WITH NAND GATES
 Under normal conditions, both inputs of the
latch (R and S) remain at 1 unless the state
has to be changed.
 To let latch in the set state, S must be 0

 To let latch in the reset state, R must be 0

 The inputs S and R must go back to 1 before


any other changes to avoid the occurrence of
the undefined state (when Q=1 and Q’=1)
 The latch goes to the set state or reset state
and stays there, even after both inputs return
to 1.
October 1, 2019 13
SR LATCH WITH NAND GATES

 When both inputs S and R are equal to 1, the


latch can be in either the set or the reset
state, depending on which input was most
recently a 0.
 Because the NAND latch requires a 0 signal
to change its state, it is sometimes referred to
as an S’R’ latch.
October 1, 2019 14
SR LATCH WITH CONTROL INPUT

 An indeterminate condition occurs when all three


inputs are equal to 1. It is difficult to ensure that
both S and R are not equal to 1 at the same time.
 Operation of the basic SR latch can be modified by
providing an additional control input that
determines when the state of the latch can be
changed.
October 1, 2019 15
D LATCH (TRANSPARENT LATCH)
D latch has only two inputs D (Data) and En 
(Enable). This circuit ensures that inputs S and
R are never equal to 1 at the same time.

October 1, 2019 16
GRAPHIC SYMBOLS FOR LATCHES

October 1, 2019
 Designated by a rectangular block.
 Normal output and complemented output
(bubble)
 For NAND gates latch, set and reset by logic
zero, hence the bubbles and bars at inputs. 17
PROBLEMS WITH LATCHES

October 1, 2019
 State transitions of the latches start as soon as the
clock pulse changes to logic 1 level.
 The new state of a latch appears at the output while
the pulse is still active.
 Combinational circuit will generate new outputs and
the state of the latch will change again within the
same clock cycle.

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