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Hardware Description Language1

HDL (Hardware Description Language) is a specialized language used to describe the structure and behavior of digital logic circuits. The two major HDLs are VHDL and Verilog. HDLs allow for simulation and synthesis of a circuit description. HDL code can be written using different description styles such as dataflow, behavioral, and structural. HDLs include operators, loops, and procedural statements to describe circuit behavior over time.

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49 views24 pages

Hardware Description Language1

HDL (Hardware Description Language) is a specialized language used to describe the structure and behavior of digital logic circuits. The two major HDLs are VHDL and Verilog. HDLs allow for simulation and synthesis of a circuit description. HDL code can be written using different description styles such as dataflow, behavioral, and structural. HDLs include operators, loops, and procedural statements to describe circuit behavior over time.

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sunil kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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HDL

(HARDWARE DESCRIPTION LANGUAGE)


Hardware description language
•In electronics a hardware description language (HDL) is a
specialized computer language .
• used to describe the structure and behaviour
of electronic circuits , and most commonly, digital
logic circuits.
•A hardware description language enables a
precise, formal description of an electronic and simulation
of an electronic circuit.
• It also allows for the synthesis of a HDL description into
a netlist (a specification of physical electronic components
and how they are connected together)
• A hardware description language looks much like
a programming language such as C it is a textual
description consisting of expressions, statements and
control structures.
• HDLs are standard text-based expressions of the structure
of electronic systems and their behaviour over time.
Like concurrent programming languages.
There are two major hardware description languages.

 Vhdl- (VHSIC Hardware Description Language) is a


hardware description language used in electronic
design automation to describe digital and mixed-
signal systems such as field-programmable gate arrays
and integrated circuits.
 Verilog- is a hardware description language (HDL)
used to model electronic systems. It is most
commonly used in the design and verification of
digital circuits at the register-transfer level.
• Simulation
– Input values are applied to the circuit
– Outputs checked for correctness
• Synthesis
– Transforms HDL code into a netlist describing the
hardware (i.e., a list of gates and the wires
connecting them)
• There are different types of description.
 Dataflow-In the data flow approach, circuits are described
by indicating how the inputs and outputs of built-in
primitive components connected together
 Behavioral -Behavioral modelling refers to a way to write
code based on its functionality: it's like writing the
algorithm that solves your problem.
 Structural- Structural modelling refers to that type of
modelling in which we simply interconnect the components
by mapping there ports by seeing the rtl diagram .
Example for data flow description (4 bit adder)
Module four_bit_adder(x,y,cin,sum,cout);
input [3:0] x,y;
input cin;
output[3:0] sum;
output cout; wire c1,c2,c3;
fa1(A[0],B[0],cin,sum[0],c1);
fa2(A[1],B[1],c1,sum[1],c2);
fa3(A[2],B[2],c2,sum[2],c3);
fa4(A[3],B[3],c3,sum[3],c4);
endmodule
Example for Structural description(Half adder)
module xor1(input a, b, output s);
xor (s, a, b);
endmodule
module and1(input a, b, output c);
and (c, a, b);
endmodule
module halfadder8 (input a, b, output s, c);
xor1 u1(a, b, s);
and1 u2(a, b, c);
endmodule
Example for behavioral description(4 bit adder)
module adder_4bit ( a ,b ,sum ,carry );
output [3:0] sum ;
reg [3:0] sum ;
output carry ;
reg carry ;
input [3:0] a ;
wire [3:0] a ;
input [3:0] b ;
wire [3:0] b ;
integer i;
reg [4:0]s;
always @ (a or b)
begin
s[0] = 0;
for (i=0;i<=3;i=i+1) begin
sum [i] = a[i] ^ b[i] ^ s[i];
s[i+1] = (a[i] & b[i]) | (b[i] & s[i]) | (s[i] & a[i]);
end
carry = s[4];
end
endmodule
operators
• Arithmetic operator
+, -, *, /, %

• Relational operator
 < less than
 > greater than
 <= less than or equal
 >= greater than or equal

• Equality operator
 a === b a equal to b
 · a !== b a not equal to b
 · a == b a equal to b
 · a != b a not equal to b
• Logical operator
 ! -logical negation
 && - logical and
 || -logical or

• Bitwise operator
 ~ negation
 & and
 | inclusive or
 ^ exclusive or
 ^~ or ~^ exclusive nor (equivalence)
• Reduction operator
 & and
 ~& nand
 | or
 ~| nor
 ^ xor
 ^~ or ~^ xnor
– Shift opearator
– << left shift
– · >> right shift
Loop statement
• Forever Statement
Continuously executes a statement
Syntax
Forever
Procedural_ statement
Example
Initial
Begin
Clock=0;
#5 forever
# 10 clock=~ clock;
end
•Repeat loop

Executes a statement a fixed number of times.


Repeat (loop _count)
Procedural_ statement
Example
Repeat (count)
Sum=sum+10;
While loop

• Executes a statement until an expression becomes false.


While(expression)
Procedural_ statement
• Example
While(By>0)
begin
Acc=Acc<<1;
By=By-1
end
•For loop

Similar to C for-statement
for (initial_assignment; condition; step_assignment)
Procedural statement
Example
begin :init_mem
reg [7:0] tempi;
for (tempi = 0; tempi < memsize; tempi = tempi + 1)
memory[tempi] = 0;
end
Procedural statement
Initial Statement
· Activated at the beginning of simulation
· Executed once
initial
begin
areg = 0; // initialize a register
for (index = 0; index < size; index = index + 1)
memory[index] = 0; // initialize a memory
end
initial
begin
inputs = 6'b000000;
#10 inputs = 6'b001011;
#10 inputs = 6'b110001;
end
Always Statement
· Activated at the beginning of simulation
· Repeats continuously throughout the whole simulation run
always
#100 clock = ~clock // creates a clock signal with #200 period
time
always
@(posedge clock) // the block below starts execution at
posedge of clock
begin
#10 a = 0; // #10 after the posedge of clock, a becomes 0
#20 b = 1; // #30 after the posedge of clock, b becomes 1
#40 b = 0; // #70 after the posedge of clock, b becomes 1
end

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