Error Detection

• Data transmission can contain errors

– Single-bit
– Burst errors of length n
(n: distance between the first and last errors in data
block)
• How to detect errors
– If only data is transmitted, errors cannot be detected
 Send more information with data that satisfies a
special relationship
 Add redundancy

Winter 2005 ECE 766 10 - 1

Computer Interfacing and Protocols
ECE
Error Detection Methods
• Vertical Redundancy Check (VRC)
– Append a single bit at the end of data block
such that the number of ones is even
 Even Parity (odd parity is similar)
0110011  01100110
0110001  01100011
– VRC is also known as Parity Check
– Performance:
• Detects all odd-number errors in a data block

Winter 2005 ECE 766 10 - 2

Computer Interfacing and Protocols
ECE
Error Detection Methods
• Longitudinal Redundancy Check (LRC)
– Organize data into a table and create a parity
for each column
11100111 11011101 00111001 10101001

11100111
11011101
00111001
10101001
10101010

11100111 11011101 00111001 10101001 10101010

Original Data LRC
Winter 2005 ECE 766 10 - 3
Computer Interfacing and Protocols
ECE
Error Detection Methods
– Performance:
• Detects all burst errors up to length n
(number of columns)
• Misses burst errors of length n+1 if there are n-1
uninverted bits between the first and last bit
• If the block is badly garbled, the probability of
acceptance is 12 n

• Checksum
– Used by upper layer protocols
– Similar to LRC, uses one’s complement
arithmetic
Winter 2005 ECE 766 10 - 4
Computer Interfacing and Protocols
ECE
Cyclic Redundancy Check
• Powerful error detection scheme
• Rather than addition, binary division is
used  Finite Algebra Theory (Galois
Fields)
• Can be easily implemented with small
amount of hardware
– Shift registers
– XOR (for addition and subtraction)

Winter 2005 ECE 766 10 - 5

Computer Interfacing and Protocols
ECE
Cyclic Redundancy Check
• Let us assume k message bits and
n bits of redundancy
xxxxxxxxxx yyyy Block of length k+n

k bits n bits
• Associate bits with coefficients of a
polynomial
1 0 1 1 0 1 1
1x6+0x5+1x4+1x3+0x2+1x+1
= x6+x4+x3+x+1

Winter 2005 ECE 766 10 - 6

Computer Interfacing and Protocols
ECE
Cyclic Redundancy Check
• Let M(x) be the message polynomial
• Let P(x) be the generator polynomial
– P(x) is fixed for a given CRC scheme
– P(x) is known both by sender and receiver
• Create a block polynomial F(x) based on
M(x) and P(x) such that F(x) is divisible by
P(x) F ( x) 0
 Q( x) 
P( x) P( x)
Winter 2005 ECE 766 10 - 7
Computer Interfacing and Protocols
ECE
Cyclic Redundancy Check
• Sending
1. Multiply M(x) by xn
2. Divide xnM(x) by P(x)
3. Ignore the quotient and keep the reminder C(x)
4. Form and send F(x) = xnM(x)+C(x)

• Receiving
1. Receive F’(x)
2. Divide F’(x) by P(x)
3. Accept if remainder is 0, reject otherwise

Winter 2005 ECE 766 10 - 8

Computer Interfacing and Protocols
ECE
Proof of CRC Generation
Prove that x n M ( x)  C ( x) is divisible by P( x)
Q( x)
P( x) x n M ( x) , remainder C ( x)
 x n M ( x)  P( x)Q( x)  C ( x)
x n M ( x)  C ( x) P( x)Q( x) C ( x)  C ( x)
 
P( x) P( x) P( x)

Remainder 0 Remainder 0
Note: Binary modular addition is equivalent to
binary modular subtraction  C(x)+C(x)=0
Winter 2005 ECE 766 10 - 9
Computer Interfacing and Protocols
ECE
 Example
• Send • Receive
– M(x) = 110011  x5+x4+x+1 (6 bits)
– P(x) = 11001  x4+x3+1 (5 bits, n = 4) 11001 1100111001
 4 bits of redundancy
11001
– Form xnM(x)  110011 0000
 x9+x8+x5+x4 11001
– Divide xnM(x) by P(x) to find C(x)
11001
100001 00000
11001 1100110000
11001 No remainder
10000  Accept
11001
1001 = C(x)
Send the block 110011 1001
Winter 2005 ECE 766 10 - 10
Computer Interfacing and Protocols
ECE
Properties of CRC
• Sent F(x), but received F’(x) = F(x)+E(x)

When will E(x)/P(x) have no remainder,

i.e., when does CRC fail to catch an error?

1. Single Bit Error  E(x) = xi

If P(x) has two or more terms, P(x) will not divide E(x)
2. 2 Isolated Single Bit Errors (double errors)
E(x) = xi+xj, i>j
E(x) = xj(xi-j+1)
Provided that P(x) is not divisible by x, a sufficient
condition to detect all double errors is that P(x) does
not divide (xt+1) for any t up to i-j (i.e., block length)
Winter 2005 ECE 766 10 - 11
Computer Interfacing and Protocols
ECE
Properties of CRC
3. Odd Number of Bit Errors
If x+1 is a factor of P(x), all odd number of bit errors
are detected

Proof:
Assume an odd number of errors has x+1 as a factor.
Then E(x) = (x+1)T(x).
Evaluate E(x) for x = 1
 E(x) = E(1) = 1 since there are odd number of terms
(x+1) = (1+1) = 0
(x+1)T(x) = (1+1)T(1) = 0
 E(x) ≠ (x+1)T(x)

Winter 2005 ECE 766 10 - 12

Computer Interfacing and Protocols
ECE
Properties of CRC
4. Short Burst Errors
(Length t ≤ n, number of redundant bits)
E(x) = xj(xt-1+…+1)  Length t, starting at bit position j
If P(x) has an x0 term and t ≤ n, P(x) will not divide E(x)
All errors up to length n are detected
5. Long Burst Errors (Length t = n+1)
Undetectable only if burst error is the same as P(x)
P(x) = xn+ … + 1 n-1 bits between xn and x0
E(x) = 1 + … + 1 must match
Probability of not detecting the error is 2-(n-1)
6. Longer Burst Errors (Length t > n+1)
Probability of not detecting the error is 2-n

Winter 2005 ECE 766 10 - 13

Computer Interfacing and Protocols
ECE
Properties of CRC
• Example:
– CRC-12 = x12+x11+x3+x2+x+1
CRC-16 = x16+x15+x2+1
CRC-CCITT = x16+x12+x5+1
– CRC-16 and CRC-CCITT catch all
• Single and double errors
• Odd number of bit errors
• Bursts of length 16 or less
• 99.997% of 17-bit error bursts
• 99.998% of 18-bit and longer error bursts
Winter 2005 ECE 766 10 - 14
Computer Interfacing and Protocols
ECE
Hardware Implementation
• Usual practice:
– After taking k data bits, n 0s are padded to the
stream, then divided by the generator
• Aim:
– Introduce the last n bits of 0s without requiring n extra
shifts
– Eliminate the need to wait for all data to enter the
system to start generating CRC
• Approach:
– Guess the next n bits of message as all 0s
– Correct the guess as the actual bits arrive

Winter 2005 ECE 766 10 - 15

Computer Interfacing and Protocols
ECE
Hardware Implementation
Circuit: 1100101
• Message = 1011011 k=7 1101 0000000000
1000
P(x) = 1101 = x3+x2+x0 n = 3 1101
Conventional 1100101 1 1010
Method: 1010
1101 1011011000 1101
1101 0 1110
1100 0110
1101 0000

Message
1 1100
0011
0100
0000 0000
0111 1 1000
0000 1000
1110 0 1101
1101 1010
0110 0010
1 0000
0000 0100
1100 1100
1101 1 1101
001 001
Winter 2005 ECE 766 10 - 16
Computer Interfacing and Protocols
ECE
Hardware Implementation
Transmit:
Data SQ Bit 2 Bit 1 Bit 0
MSB
1 1 0 0 0
Serial Quotient (SQ) 0 1 1 0 1

Message
x3 x2 1 0 1 1 1
x0 1 0 1 1 0
+ 2 + 1 0 0 1 1 0 0
1 0 1 0 1
Data
1 1 0 1 0
LSB
Input 0 0 1
CRC
k shifts later, CRC is in register Send MSB first
Shift out (without any XOR) in n shifts

Winter 2005 ECE 766 10 - 17

Computer Interfacing and Protocols
ECE
Hardware Implementation
Receive:
Data SQ Bit 2 Bit 1 Bit 0
MSB
1 1 0 0 0
Serial Quotient (SQ) 0 1 1 0 1

Message
x3 x2 1 0 1 1 1
x0 1 0 1 1 0
+ 2 + 1 0 0 1 1 0 0
1 0 1 0 1
Data
1 1 0 1 0
LSB
Input
MSB
0 0 0 0 1
CRC 0 0 0 1 0
n+k shifts later, remainder is 0 1 0 1 0 0
Data accepted 0 0 0
LSB

Winter 2005 ECE 766 10 - 18

Computer Interfacing and Protocols
ECE
 Hardware Implementation
x2
A x0
+

+ 2
1 0
Data In
A
Control Line A:
A 1: Make/Test CRC
0: Shift Out CRC

Data OK

For Transmitting:
Data Out Assert A true while feeding k bits of message
Assert A false for n clock cycles to output CRC

For Receiving:
A Assert A true while feeding k+n bits of message and CRC
Ignore Data Out, check Data OK for correctness

Winter 2005 ECE 766 10 - 19

Computer Interfacing and Protocols
ECE