ADC 0808/0809
PIN DESCRIPTION
• I/P0-I/P7 : Analog Inputs
• ADD A,B,C : Address lines for selecting analog inputs
• O7-O0 : Digital 8-bit output with O7 – MSB
• SOC : Start of conversion signal pin
• EOC : End of conversion signal pin
• OE : output latch enable pin, if high enable output
• CLK : clock input for ADC
• Vcc, GND : supply pins +5V and GND
• Vref+, Vref- : Reference voltage positive (+5V max) and
reference voltage negative (0 V min)
• ALE : It is required to load the selected address lines to
into the ADC
BLOCK DIAGRAM OF ADC 0808
TIMING DIAGRAM
ADC INTERFACING
• Ensure the stability of analog input, applied
to the ADC
• Issue start of conversion (SOC) pulse to the
ADC
• Read end of conversion (EOC) signal to
mark the end of conversion process
• Read digital data output of the ADC as
equivalent digital output
PROBLEM:
Interface ADC0808 with 8086 using 8255 ports. Use
Port A of 8255 for transferring digital data output of
ADC to the CPU and Port C for control signals. Assume
that an analog i/p is present at I/P2 of the ADC and a
clock input of suitable frequency is available for
ADC.Draw the schematic and write required ALP.
8253 / 8254 Programmable Interval
Timer
• It is used to generate an accurate arbitrary time delays
• It is used to bring down the frequency to the desired level
• Three counters inside 8253/8254. Each works
independently and is programmed separately to divide the
input frequency by a number from 1 to 65536.
• Maximum count rate of 10 MHZ
• There are 4 port address needed for a single 8253/8254,
given by A0, A1, and CS
CS A1 A0 Select
0 0 0 Counter 0
0 0 1 Counter 1
0 1 0 Counter 2
0 1 1 Control Reg.
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
• Each of the three counter has 3 pins associated
– CLK: input clock frequency
• A square wave of 33% duty cycle
• 8253: 0 ~ 2 MHz, 8254: 0 ~ 8 MHz
– OUT: can be square wave, or one shot
– GATE: Enable (high) or disable (low) the counter
• Data Pins: (D0 ~ D7)
– Allow the CPU to access various registers inside the
8253/54 for both read and write operations. RD and
WR are connected to IOR and IOW of control bus.
8253 / 8254 Timer
• Each of the three counters must be programmed
separately
• Control byte must be first written into the
control register. The 8253/54 must be initialized
before use
• The programmer can not only write the value of
the divisor into the 8253/54, but read the content
of the counter at any given time as well
• All counters are down counters.
8253 / 8254 Timer
• To program a given counter to divide the CLK
input frequency, one must send the divisor to
that specific counter’s register.
• Although all three counters share the same
control register, the divisor registers are separate
for each counter
• Example: given the port addresses for 8253/54:
Counter 0: 94H Counter 1: 95H
Counter 2: 96H Control Reg: 97H
Operating modes of 8254
• Mode 0 (Interrupt on terminal count)
• Mode 1(Programmable monoshot)
• Mode 2 (Rate generator)
• Mode 3 (Square wave generator)
• Mode 4 (Software triggered strobe)
• Mode 5 ( Hardware triggered strobe)
Mode 0 ─ Interrupt on Terminal
Count
• Initially the output is low after the mode is set. The output
remains LOW after the count value is loaded into the
counter.
• The process of decrementing the counter continues till the
terminal count is reached, i.e., the count become zero and
the output goes HIGH and will remain high until it reloads
a new count.
• The GATE signal is high for normal counting. When
GATE goes low, counting is terminated and the current
count is latched till the GATE goes high again.
• It is used to generate an interrupt to the microprocessor
after a certain interval.
Mode 1 – Programmable One
Shot
• It can be used as a mono stable multi-vibrator.
– The duration of quasi-stable state is decided by the
count loaded in the count register
• The gate input is used as a trigger input in this mode.
• The output remains high until the count is loaded and a
trigger is applied.
• If another count is loaded when the output is already
low, it does not disturb the previous count till a new
trigger pulse is applied at the GATE input.
Mode 2 – Rate Generator/Divide by
N Counter
• After N pulses ( N-count value), the output becomes
low only for one clock cycle.
• The count is reloaded and again the output becomes
high and remains high for N clock pulses.
• Whenever the count becomes zero, another low pulse
is generated at the output and the counter will be
reloaded.
• The counting is inhibited when GATE becomes low.
Mode 3 – Square Wave
Generator
• This mode is similar to Mode 2 except the
output remains low for half of the timer
period and high for the other half of the
period.
Mode 4 − Software Triggered
Mode
• In this mode, the output will remain high
until the timer has counted to zero, at which
point the output will pulse low and then go
high again.
• The count is latched when the GATE signal
goes LOW.
• On the terminal count, the output goes low
for one clock cycle then goes HIGH. This
low pulse can be used as a strobe.
Mode 5 – Hardware Triggered
Mode
• This mode generates a strobe in response to an
externally generated signal.
• This mode is similar to mode 4 except that the
counting is initiated by a signal at the gate input,
which means it is hardware triggered instead of
software triggered.
• After it is initialized, the output goes high.
• When the terminal count is reached, the output
goes low for one clock cycle.
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
