VHDL PROGRAMMING

(VHSIC HARDWARE DESCRIPTION LANGUAGE)

Very High Speed Integrated

Circuit
HARDWARE DESCRIPTION LANGUAGE
(HDL)
• Language to describe hardware
• Two popular languages
• VHDL: Very High Speed Integrated Circuits Hardware Description
Language
• Developed by DOD from 1983
• IEEE Standard 1076-1987/1993/200x
• Based on the ADA language
• Verilog
• IEEE Standard 1364-1995/2001/2005
• Based on the C language
APPLICATIONS OF HDL
• Model and document digital systems
• Different levels of abstraction
• Behavioral, structural, etc.

• Verify design
• Synthesize circuits
• Convert from higher abstraction levels to lower abstraction levels
VHDL
• VHDL stands for very high-speed integrated circuit
hardware description language. It is a programming
language used to model a digital system by dataflow,
behavioral and structural style of modelling.
LIBRARY
• Describing a Design declarations
Basic
• Library ENTITY VHDL code
• Entity declaration
• Generic ARCHITECTURE
• Port
• Downto LIBRARY
• Map
• Architecture PACKAGE
• Begin •• FUNCTIONS
FUNCTIONS
• end •• COMPONENTS
COMPONENTS
•• PROCEDURES
PROCEDURES
•• CONSTANTS
CONSTANTS
•• TYPES
TYPES
VHDL
library IEEE;
use
IEEE.STD_LOGIC_1164.ALL
;
Library – “ library ”
• Used to designate the library used in your
design
entity entity_name is
port ( port_ID1: I/O option signal_type;
port_ID2: I/O option signal_type;
);
end entity_name;

Entity – “ entity “
• Defines the input and output of your
design. • Name of the circuit
• User-defined
• Filename same as circuit name
recommended
• Example:
• Circuit name: entity_name
• File name : entity_name.vhd
VHDL •• we
we indicate
the
indicate the
the input
input and
“Library”.
“Library”.
the data
data type
and output
type available
output ports
available at
ports an
an in
in
at

•• where
where wewe used
used std_logic
std_logic for
for all
all port
Port – “port” data types.
data types.
port

• Define the interference I/O ’s of the design

Port ( inp1, inp2: in std_logic; --Input
ports
outp1, outp2, outp3: out std_logic ); --Output
ports
Std_logic –
• the data type used for the ports is std_logic defined in the package
IEEE.std_logic_1164.all. For std_logic data type, there are 8 possible
values available

• ‘X’ Unknown Represent a

• ‘0’ Logic 0 single bit
• ‘Z’ High Impedance
• ‘W’ Weak Unknown
• ‘L’ Weak Low
• ‘H’ Weak High
• ‘-’ Don’t Care
VHDL Represent an array of standard
logic value
std_logic_vector –
• The std_logic_vector data type is defined in the library IEEE.std_logic_1164.all. If an I/O
port has data type of std_logic_vector, it means
Port ( inp1: that the I/O port has(3
in std_logic_vector a number
downto of
std_logic values. 0)
inp2: in std_logic_vector (3 downto
0)
outp1: out std_logic_vector (4
downto 0)
bit_vector- outp2: out std_logic_vector (4
downto 0) );
• bit_vector is defined in standard package, we don’t need to include any
header file.
Port ( inp1: in bit_vector (3 downto 0)
inp2: in bit_vector (3 downto 0)
outp1: out bit_vector (4 downto 0)
outp2: out bit_vector (4 downto 0) );
 VHDL
Integer range -

The data type integer is defined in standard package; we don’t need to

include any header file. However,
Portit(isinp1:
logical to indicate
in integer a range
range 0 tofor the
integer data type. 15;
inp2: in integer range 0 to
15;
outp1: out integer range 0
to 31;
Natural range - outp2: out integer range 0
to 31 );
Port the
The data type natural is used to indicate ( inp1: in naturalintegers.
non-negative range 0
to 15;
inp2: in natural range 0 to
15;
outp1: out natural range 0
to 31;
outp2: out natural range 0
to 31 );
 VHDL
Unsigned data type
• Similar to a Standard logic vector can only represent positive (non-negative) number.
• Advantage of able to use the “+” Port
& “-” (, inp1:
less then/greater thendownto
in unsigned(3 operations.
0);
inp2: in unsigned (3 downto
0);
outp1: out unsigned (4
downto 0);
outp2: out unsigned (4
Signed data type downto 0) );
• Similar to a Standard logic vector can represent both positive and negative number .

Port ( inp1: in signed(3 downto 0);

inp2: in signed (3 downto 0);
outp1: out signed (4 downto
0);
outp2: out signed (4 downto
0) );
 VHDL
Architecture
• This is where actual design goes. architecture architecture_name of
entity_name is
Declarations
begin
Statements
end [architecture] [architecture_name];

The last line of the architecture can be either “end architecture” or

“end
architecture_name” or “end architecture architecture_name” or just
“end”.
architecture my_arc of architecture my_arc of
my_entity is my_entity is
begin begin
end architecture; end my_arc;
 VHDL
Data Objects

• A data object has a name and data type. The general syntax for the use of the data
object is as

data object object name : data type := initial value;

• data object can be signal, variable, or constant.

• The data type can be any data type available in VHDL programming, such as bit,
std_logic, integer, unsigned, signed, std_logic_vector, bit_vector, etc.
• Constant object
• Signal object
• Variable object
 VHDL
Constant Object

• The constant objects are usually declared in the declarative part of the
architecture, entity, package, process, procedure and function. However, it can
also be declared in the package body, block, generate.

• The value of the constant object cannot be changed through the program. Its
syntax is as follows constant name : data type := initial value;

constant my_constant: integer:=32;

constant my_flag: std_logic:=’1’;
constant my_vector : std_logic_vector(3
downto 0):= "1010";
 VHDL
Signal object

• The signal objects can be declared in the declarative part of the architecture. On the
other hand, the variable objects can be declared inside the sequential program
segments, like process, procedure, function.

• Its syntax is as follows

signal name : data type := initial value;
Signal my_number: integer;
Signal my_bit: bit:=’1’;
Signal my_vector : std_logic_vector(3 downto
0):= "1010";
 VHDL
Variable Object

• Variable object declarations may or may not include an initial value. Variable
objects are employed in sequential program units, such as function, procedure,
and process.

• Its syntax is as follows

variable name : data type := initial value;
Variable my_number: natural;
Variable my_logic: std_logic:=’1’;
Variable my_vector : std_logic_vector(3 downto
0):= "1110";
 VHDL
VHDL Operators
• Assignment Operators

• Logical Operators

• Relational Operators

• Arithmetic Operators

• Concatenation Operator

Assignment Operators
• Operator “:=”
• We use operator “:=” for either initial value assignment or to assign a
value to a variable, constant or generic.
• Note that “:=” is used for signal objects only for initial value
assignment. It is not used for signal objects in any other cases.
VHDL
• Operator “<=”
• We use the operator “<=” to assign a value to a signal object.
• Operator “=>” and “others” keyword
• We use operator “=>” to assign values to vector elements. The operator
“=>” is usually employed with the reserved word others which indicates the
index values of the unassigned vector elements.

Logical Operators and Shift Operators

• The logical operators are used for data types bit, std_logic,
std_logic_vector, std_ulogic, std_ulogic_vector, and Boolean. Logical
operators are used for the implementation combinational logic circuits.

Logical operators and, or, nand, nor, xor, xnor, not

Shift operators sll, srl, sla, sra, rol, ror
 If
x <=
VHDL “0101011110”
then
Shift Operators y <= x sll 2
produces
• SLL: Shift Left Logical y <=
• The bits are shifted to the left and new “0101111000”
positions are filled by zeros.

SRL: Shift Right Logical

• The bits are shifted to the right and new positions are filled by zeros.

If
x <= “11111110”
then
y <= x sla 3
produces
y <=
“11110000”
 VHDL If
x <= “01111111”
then
y <= x sra 3
produces
y <=
SRA: Shift Right Arithmetic “00001111”
• The bits are shifted to the right and new positions are filled by the value of the leftmost bit.

SRL: Shift Right Logical

• The bits are shifted to the right and new positions are filled by zeros.
If
x <=
“101011110”
then
y <= x srl 2
produces
y <=
“001010110”
GENERAL GUIDELINES AND PROCEDURES TO
CONDUCT AN EXPERIMENT
• Each experiment has to be first simulated using XILINX, both with
VHDL and VERILOG.
• Then the circuit has to be tested using a test bench in simulation
level.
• After simulation is over, the circuit has to be implemented on FPGA
Spartan -3A start-up kit.
• Steps:
• Design description/Design entry (Design is described in various levels of
abstraction).
• Functional verification (functionality of the design is tested by test
benches) .
• Synthesis (converting the design description in to gate level net-list)
• Implementation (The synthesized circuit is mapped on to FPGA via
proper interface and programming)
 SIMULATION
• Creating a new project
To create a new project:

1). Select File > New Project... The New Project Wizard appears.
Creating a new project

2). Type entity_name in the Project Name field.

Creating a new project
3). Fill in the properties as shown below:
4). Click Next, then Finish in the New project Wizard
Create an HDL Source

1). Click the New Source button in the New Project Wizard.
Create an HDL Source
2). Select VHDL Module as the source type.
3). Type in the file name entity_name.
4). Click Next.
 Create an HDL Source
5). The source file containing the entity/architecture pair displays in the Workspace, and the
entity_name displays in the Source tab, as shown below.
6). Click Next, then Finish in the New Source Wizard - Summary dialog box to complete
the new source file template.
 Create an HDL Source

7). The source file containing the entity/architecture pair displays in the Workspace, and the
counter displays in the Source tab, as shown below
Create an HDL Source
ARCHITECTURE architecture_name OF entity_name IS
[declarations]
BEGIN
(code)
END architecture_name;