16EI204

DIGITAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUIT

Module-II
Dr.V.Radhika
A.P.(Sl.Gr)/EIE
 Course Outcome & Syllabus
COURSE OUTCOME
CO2:Design the combinational logic circuits

SYLLABUS
COMBINATIONAL LOGICCIRCUIT

Analysis and design of combinational logic circuits:

Arithmetic units- Decoders - Encoders - Multiplexers-
Demultiplexers - Code converters - Parity circuits -
Comparators-Applications of combinational logic circuits.
BCD Adder
 BCD Adder
 When the sum of two digits is less than or equal
to 9 then the ordinary 4-bit adder can be used
 But if the sum of two digits is greater than 9 then
a correction must be added “I.e adding 0110”
 We need to design a circuit that is capable of
doing the correct addition
 BCD Adder
 The cases where the sum of two 4-bit numbers is greater
than 9 are in the following table:

S4 S3 S2 S1 S0
0 1 0 1 0 10
0 1 0 1 1 11
0 1 1 0 0 12
0 1 1 0 1 13
0 1 1 1 0 14
0 1 1 1 1 15
1 0 0 0 0 16
1 0 0 0 1 17
1 0 0 1 0 18
 BCD Adder
 Whenever S4=1 (sums greater than 15)
 Whenever S3=1 and either S2 or S1 or both are 1 (sums 10 to
15)
 The previous table can be expressed as:
X = S4 + S3 ( S2 + S1)
So, whenever X = 1 we should add a correction of 0110 to the
sum.
Inputs:[A]=0101, [B]= 0011, Co=0
0011

0101
0 1 0 0 0

0 0

1000

1
1 0 0 0

0000
Inputs:[A]=0111, [B]= 0110, Co=0
0110

0111
0 1 1 0 1

1 1

1101

1
0 0 1 1

0110
Carry-Lookahead Adders
 Carry-Lookahead Adders
 This is the addition technique that eliminates the problem
due to inter stage carry delay.
 The look ahead carry addition will therefore speed up the
addition process.
 The carry-lookahead adder calculates one or more carry bits
before the sum, which reduces the wait time to calculate the
result of the larger-value bits of the adder.
 The adder with look ahead carry needs additional hardware
but the speed of thus adder is independent of the number of
bits.
 Basic Signals
Generate signal: gi = xiyi
Propagate signal: pi = xi  yi

cout =1 given cin = 1

Carry recurrence

ci+1 = gi + cipi = gi + ci ti
 4-bit Carry-Lookahead Adder
c4 = g3 + g2 p3 + g1 p2p3 + g0p1p2p3 + c0p0p1p2p3

c3 = g2 + g1 p2 + g0 p1p2 + c0p0p1p2

c2 = g1 + g0 p1 + c0p0p1

c1 = g0 + c0 p0

s0 = x0  y0  c0 = p0  c0 s1 = p 1  c 1
s2 = p 2  c 2 s3 = p 3  c 3
 4-bit Carry-Lookahead Adder
c4 = g3 + c3p3 3 gates less

c3 = g2 + g1 p2 + g0 p1p2 + c0p0p1p2

c2 = g1 + g0 p1 + c0p0p1

c1 = g0 + c0 p0

s0 = x0  y0  c0 = p0  c0 s1 = p 1  c 1
s2 = p 2  c 2 s3 = p3  c3
 4-bit Lookahead Carry Generator
Equations

ci+3 = gi+2 + gi+1 pi+2 + gi pi+1pi+2 + cipipi+1pi+2

ci+2 = gi+1 + gi pi+1 + cipipi+1

ci+1 = gi + ci pi

g[i..i+3] = gi+3 + gi+2 pi+3 + gi+1 pi+2 pi+3 + gi pi+1 pi+2 pi+3

p[i..i+3] = pi pi+1 pi+2 pi+3

4-bit Lookahead Carry Generator
Schematic
 Advantages

 Reduce the Propagation time.

 It is fastest addition logic.
 For very large numbers (hundreds or even thousands of bits)
look ahead carry logic does not become any more complex,
because more layers of super groups and supersupergroups
can be added as necessary.
Decoder
 Decoders
 A decoder has
 N inputs
 2N outputs
 A decoder selects one of 2N outputs by decoding the binary
value on the N inputs.
 The decoder generates all of the minterms of the N input
variables.
 Exactly one output will be active for each combination of
the inputs.

What does “active” mean?

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 Decoders
W = A'.B'
Out0 W
B I0 Out1 X X = A.B'
A I1 Out2 Y Y = A'.B
Out3 Z
msb Z = A.B
Active-high outputs

A B W X Y Z
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

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 Decoders
W = (A'.B')'
Out0 W
B I0 Out1 X X = (A.B')'
A I1 Out2 Y Y = (A'.B)'
Out3 Z
msb Z = (A.B)'
Active-low outputs

A B W X Y Z
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

21 ECE 331 - Digital System Design Fall 2010

 msb
Decoders

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 Decoder with Enable
Out0 W
B I0
high-level Out1 X
enable A I1
Out2 Y
Out3 Z
Enable En

En A B W X Y Z
1 0 0 1 0 0 0
1 0 1 0 1 0 0
enabled
1 1 0 0 0 1 0
1 1 1 0 0 0 1
disabled 0 x x 0 0 0 0

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 Encoders

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 Encoders
 An encoder has
 2N inputs
 N outputs
 An encoder outputs the binary value of the selected (or active)
input.
 An encoder performs the inverse operation of a decoder.
 Issues
 What if more than one input is active?
 What if no inputs are active?

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 Encoders
D I0
C I1 Out0 Z
Out1 Y
B I2
A I3

A B C D Y Z
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

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 Priority Encoders
 If more than one input is active, the higher-order input has
priority over the lower-order input.
 The higher value is encoded on the output
 A valid indicator, d, is included to indicate whether or not the
output is valid.
 Output is invalid when no inputs are active
 d=0
 Output is valid when at least one input is active
 d=1

Why is the valid indicator needed?

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 Priority Encoders
msb

Valid bit

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 Multiplexers

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 Multiplexers
 A multiplexer has
 N control inputs
 2N data inputs
 1 output
 A multiplexer routes (or connects) the selected data input to
the output.
 The value of the control inputs determines the data input
that is selected.

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 Multiplexers

Data
inputs
Z = A′.I0 + A.I1
Control
input

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 Multiplexers
A B F
0 0 I0
0 1 I1
1 0 I2
1 1 I3

MSB LSB

Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

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 Multiplexers
A B C F
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

MSB LSB
Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +
A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3

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 Multiplexers

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 Demultiplexers

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 Demultiplexers
 A demultiplexer has
 N control inputs
 1 data input
 2N outputs
 A demultiplexer routes (or connects) the data input to the
selected output.
 The value of the control inputs determines the output that is
selected.
 A demultiplexer performs the opposite function of a
multiplexer.

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 Demultiplexers
Out0 W W = A'.B'.I
Out1 X
I In X = A.B'.I
Out2 Y
Out3 Z Y = A'.B.I
S1 S0 Z = A.B.I

A B
A B W X Y Z
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I

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Code converters
 CODE CONVERTERS

 A code converter is a logic circuit that changes data presented in

one type of binary code to another type of binary code, such as
BCD to binary, BCD to 7segment, binary to BCD, BCD to
XS3, binary to Gray code, and Gray code to binary.

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 BCD-to-Binary Conversion

One method of BCD-to-Binary code conversion uses adder

circuits :
1. The value, or weight, of each bit in the BCD number is
represented by a binary number

2. All of the binary representations of the weights of bits that are 1s

in the BCD number are added

3. The result of this addition is the binary equivalent of the BCD

number

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 Contd...
For example, 4610 is represented as

 The MSB has a weight of 10, and the LSB has a weight of 1.

 So the most significant 4bit group represents 40, and the least
significant 4bit group represents 6 as in Table.

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 Example :
Convert the BCD equivalent of 26 to binary.

Solution

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 FOUR BIT BINARY TO GRAY CODE
TRUTH TABLE:
CONVERTER
INPUT ( BINARY) OUTPUTS (GRAY CODE)
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
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 FOUR BIT BINARY TO GRAY CODE CONVERTER
Simplification using K-maps:

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 FOUR BIT BINARY TO GRAY CODE CONVERTER

Logic Diagram:

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 FOUR BIT GRAY CODE TO BINARY CONVERTER
 Truth Table:

INPUT ( GRAY CODE) OUTPUTS (BINARY )

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
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 FOUR BIT GRAY CODE TO BINARY CONVERTER
Simplification using K-Maps:

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 FOUR BIT GRAY CODE TO BINARY CONVERTER
Simplification using K-Maps:

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 FOUR BIT GRAY CODE TO BINARY CONVERTER

Logic Diagram:

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 BCD to XS 3 code converter
TRUTH TABLE FOR BCD TO XS3 CODE CONVERTER:

Input ( Std BCD code) Output ( XS3 Code)

A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X
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 BCD to XS 3 code converter- Design (2)...

K-maps for simplification and simplified Boolean expressions

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 BCD to XS 3 code converter- Design (3)...

 After the manipulation of the Boolean expressions for

using common gates for two or more outputs, logic
expressions can be given by
z=D’
y=CD+C’D’ = (C+D)’
x= B’C + B’D + BC’D’ = B’(C+D) + BC’D’
w= A + BC + BD = A + B (C+D)

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 BCD to XS 3 code converter

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COMPARATORS
 COMPARATORS
 Comparator is a combinational logic circuit that
compares the magnitudes of two binary quantities to
determine which one has the greater magnitude.

 In other word, a comparator determines the relationship

of two binary quantities.

 A exclusiveOR gate can be used as a basic

comparator.

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  If two input bits are not equal, its output is a 1. But if
two input bits are equal, its output is a 0.
 So exclusiveOR gate can be used as a 2bit Comparator.

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 Contd...
 There are two different types of output relationship between
the two binary quantities;

 Equality output indicates that the two binary numbers being

compared is equal (A = B) and

 Inequality output that indicates which of the two binary

number being compared is the larger.

 That is, there is an output that indicates when A is greater than

B (A > B) and an output that indicates when A is less than B (A
< B).
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 4bit magnitude comparator
The 74LS85 compares two unsigned 4-bit binary
numbers , the unsigned numbers are A3, A2, A1, A0 and B3,
B2, B1, B0.

Cascading Outputs
Inputs

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 It has three active-HIGH outputs

Start with most significant bit in each number to

determine the inequality of 4-bit binary numbers A
and B
 Output A<B will be HIGH if A3=0, and B3=1
 Output A>B will be HIGH if A3=1, and B3=0
 If A3=0, and B3=0 or A3=1, and B3=1, then examine
the next lower order bit position for an
inequality.Only when all bits of A=B, output A=B will
be HIGH
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 Example: Determine the A=B, A>B, and A<B outputs for the input numbers shown on the 4-bit
comparator as given below.

Solution: The number on the A inputs is 0110 and the number on the B inputs is 0011. The A > B output is
HIGH and the other outputs (A=B and A<B) are LOW

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61
 Magnitude Comparator
 A = a3a2a1a0 B = b3b2b1b0
 Xi = ai.bi + ai'.bi' = ai xnor bi (equivalence)

 (A = B): X3.X2.X1.X0
 (A > B): a3b3' + X3a2b2' + X3X2a1b1' + X3X2X1a0b0'

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 Magnitude Comparator
 A = a3a2a1a0 B = b3b2b1b0
 Xi = ai.bi + ai'.bi' = ai xnor bi (equivalence)

 (A = B): X3.X2.X1.X0
 (A > B): a3b3' + X3a2b2' + X3X2a1b1' + X3X2X1a0b0'
 (A < B): a3'b3 + X3a2'b2 + X3X2a1'b1 + X3X2X1a0'b0

63 ECE 301 - Digital Electronics

 Magnitude Comparator

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