Module 1.

Basic Structure of Computers

Chapter 1:
Basic Structure of Computer

 Functional Units. (Out of syllabus)

 Basic Operational Concepts
 Bus Structures,
 Performance –
 Processor Clock,
 Basic Performance Equation,
 Clock Rate,
 Performance Measurement.
Chapter 2:
Machine Instructions and Programs
 Memory Location and Addresses,
 Memory Operations,
 Instructions and Instruction Sequencing,
 Addressing Modes,
 Assembly Language,
 Basic Input and Output Operations,
 Stacks and Queues,
 Subroutines,
 Additional Instructions,
 Encoding of Machine Instructions
Basic Structure of Computer

Module 1 Chapter 1
Functional Units
 Arithmetic
Input and
logic

Memory

Output Control

Input/ Output Processor

Figure 1.1. Basic functional units of a computer.

Input Unit
 Computers accept coded information through input
units, which read the data.
 Whenever a key is pressed, the corresponding letter
or digit is automatically translated into its
corresponding binary code and transmitted over a
cable to either the memory or the processor.
 Some input devices are
 Joysticks
 Trackballs
 Mouses
 Microphones a
 Memory Unit:
 It stores the programs and data.
 There are 2 types of storage classes
 Primary
 Secondary
 ALU

 Mostcomputer operations are

executed in ALU.
Output Unit

 Its function is to send the processed

results to the outside world.
 eg.Printer
 Control Unit
 The operations of Input unit, output unit, ALU are
co-ordinate by the control unit.
 The control unit is the Nerve centre that sends
control signals to other units and senses their
states.
 Data transfers between the processor and the
memory are also controlled by the control unit
through timing signals.
The operation of computers are,
 The computer accepts information in the form of
programs and data through an input unit and
stores it in the memory.
 Information stored in the memory is fetched,
under program control into an arithmetic and logic
unit, where it is processed.
 Processed information leaves the computer
through an output unit.
 All activities inside the machine are directed by
the control unit.
Basic Operational
Concepts
Review
 Activity in a computer is governed by instructions.
 To perform a task, an appropriate program
consisting of a list of instructions is stored in the
memory.
 Individual instructions are brought from the memory
into the processor, which executes the specified
operations.
 Data to be used as operands are also stored in the
memory.
A Typical Instruction
 Add LOCA, R0
 Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
 Place the sum into register R0.
 The original contents of LOCA are preserved.
 The original contents of R0 is overwritten.
 Instruction is fetched from the memory into the
processor – the operand at LOCA is fetched and
added to the contents of R0 – the resulting sum is
stored in register R0.
Separate Memory Access and
ALU Operation
 Load LOCA, R1
 Add R1, R0
 Whose contents will be overwritten?
Connection Between the Processor and
the Memory
Registers
 Instruction register (IR)
 Program counter (PC)
 General-purpose register (R0 – Rn-1)
 Memory address register (MAR)
 Memory data register (MDR)
Typical Operating Steps
 Programs reside in the memory through input
devices
 PC is set to point to the first instruction
 The contents of PC are transferred to MAR
 A Read signal is sent to the memory
 The first instruction is read out and loaded
into MDR
 The contents of MDR are transferred to IR
 Decode and execute the instruction
Typical Operating Steps
(Cont’)
 Get operands for ALU
 General-purpose register
 Memory (address to MAR – Read – MDR to ALU)
 Perform operation in ALU
 Store the result back
 To general-purpose register
 To memory (address to MAR, result to MDR – Write)
 During the execution, PC is
incremented to the next instruction
Interrupt
 Normal execution of programs may be preempted if
some device requires urgent servicing.
 The normal execution of the current program must
be interrupted – the device raises an interrupt
signal.
 Interrupt-service routine
 Current system information backup and restore (PC,
general-purpose registers, control information,
specific information)
Bus Structures
 There are many ways to connect different
parts inside a computer together.
 A group of lines that serves as a
connecting path for several devices is
called a bus.
 These lines carry data or address or control
signal.
 There are 2 types of Bus structures.
 Single Bus Structure
 Multiple Bus Structure
Single Bus Structure
 Single-bus Structure
 It allows only one transfer at a time.
 It costs low.
 It is flexible for attaching peripheral
devices.
 Its Performance is low.
Multiple Bus Structure
(Module 5)

 It allows two or more transfer at a time.

 It costs high.
 It provides concurrency in operation.
 Its Performance is high.
Speed Issue of BUS
 Different devices have different
transfer/operate speed.
 If the speed of bus is bounded by the slowest
device connected to it, the efficiency will be
very low.
 How to solve this?
 A common approach – use buffers.
Performance
 Performance
 The most important measure of a computer is how
quickly it can execute programs.
 Three factors affect performance:
1. Hardware design
2. Instruction set
3. Compiler (High Level language) (not discussed)

Processor time to execute a program depends on the

hardware involved in the execution of individual machine
instructions.
Cache to improve performance
What is cache ?
How cache is involved in execution of program?

Main Cache
memory memory Processor

Bus
 The processor and a relatively small cache
memory can be fabricated on a single
integrated circuit chip.

 Speed, faster than main memory.

 Cost is high.
 Processor Clock
Keywords: Clock, clock cycle, and clock rate

 Processor circuits are controlled by a timing

signal called clock.

 Clock defines regular time interval called clock

cycle. (Clock Period) ( Measured in Seconds)
 The execution of each instruction is divided into
several basic steps, each of which completes in
one clock cycle.
• If length P is one clock cycle, its inverse is clock
rate.

• Measured as “clock cycles per second”

OR Hertz (Hz)
• Today's computers have clock rate, few 100
millions to billion cycles per second.
• So one million is denoted as Mega(M) and one
Billion as Giga (G)
• For example,
500 million cycles per seconds (Hz) is denoted
as 5MHz
1250 million cycles per second(Hz) is denoted
as
 Problems
• If CPU clock rate: 200 MHz. Find clock cycle.
R=1/P
P=1/R
P = 1/(200x10+6)
P= 5x10-9 Seconds
P= 5ns
 Problems
• If clock cycle of a processor is 0.8ns, Find CPU
clock rate.
R=1/P
R = 1/(0.8x10-9)
R= 1.25x10+9 Hz
R= 1.25 GHz

• If clock cycle of a processor is 2ns, Find CPU

clock rate.
 Basic Performance Equation
 T – processor time required to execute a program that has been
prepared in high-level language

 N – number of actual machine language instructions needed to

complete the execution (note: loop)

 S – average number of basic steps needed to execute one machine

instruction. Each step completes in one clock cycle

 R – clock rate
N S
T 
R
Basic Performance Equation

How to improve T?
To achieve high performance

 Find ways to reduce T.

means reduce N and S and Increase R.
 N can be reduced when source program has
fewer instruction.
 S can be reduced if instructions have smaller
no.of basic steps.
 R can be increased using higher frequency
clock.
Think
 Which processor provide better performance?
one with 900 MHz or one with 700 MHz ?

Can not say because their S value may be

different.
Clock Rate
 Increase clock rate
 Improve the integrated-circuit (IC)
technology to make the circuits faster
 Reduce the amount of processing
done in one basic step (however, this
may increase the number of basic
steps needed)
 Performance Measurement
 T is difficult to compute.

 Measure computer performance using benchmark programs.

 System Performance Evaluation Corporation (SPEC) selects and

publishes representative application programs for different application
domains, together with test results for many commercially available
computers.

 Compile and run

Example:
SPEC2000
Ultra SPARC 10
 Running time on the reference computer
SPEC rating 
Running time on the computer under test
n 1
SPEC rating  ( SPECi ) n

i 1
Machine Instructions and
Programs
Module 1 Chapter 2
 Memory Locations and
Addresses
 Byte Addressability
 Endian Formats
 Word Alignment
 Accessing number, character and string
Memory Location and Addresses

n bits
first word
 Memory consists
second word
of many millions of
storage cells,
•
each of which can •
•
store 1 bit.
 Data is usually i th word
accessed in n-bit
groups. n is called •
word length. •
•

last word

Figure 2.5. Memory words.

Memory Location and Addresses

 32-bit word length example

32 bits

b31 b30 b1 b0

•
•
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Location and Addresses

 To retrieve information from memory, either for one

word or one byte (8-bit), addresses for each location
are needed.
 A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240
Byte Addressability

Unique and
continuous
addresses are
assigned to
successive
bytes in the
memory.
Byte Addressability

 It is impractical to assign distinct addresses to

individual bit locations in the memory.

 The most practical assignment is to have

successive addresses refer to successive byte
locations in the memory – byte-addressable
memory.

 Byte locations have addresses 0, 1, 2, … If word

length is 32 bits, they successive words are
located at addresses 0, 4, 8,…
Word Aligned Memory

If word size is
n bytes, and
every word
starts at the
address
multiple of n.
Word Aligned Memory

 Address ordering of bytes

 Word alignment
 Words are said to be aligned in memory if they
begin at a byte addr. that is a multiple of the num of
bytes in a word.
 16-bit word: word addresses: 0, 2, 4,….

 32-bit word: word addresses: 0, 4, 8,….

 64-bit word: word addresses: 0, 8,16,….

Hint: If word size is 4 bytes, every word address ends
with 00 in binary.
Big-Endian and Little-Endian Assignments
Big-Endian: lower byte addresses are used for the most
significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses
are used for the less significant bytes of the word
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •
k k k k k k k k k k
2-4 2-4 2-3 2- 2 2 - 1 2-4 2- 1 2 - 2 2 -3 2-4

(a) Big-endian assignment (b) Little-endian assignment

Access numbers, characters, and
character strings

String: Starting address of string

is given and end of the string is
identified using special character.
Memory Operation
 Load (or Read or Fetch)
 Copy the content. The memory content doesn’t change.
 Address – Load
 Registers can be used
 Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used
 Instruction and
Instruction Sequencing

 Register Transfer Notations

 Assembly Language Notations
 Basic Instruction Types
 Instruction Execution and Strait-line Sequencing
“Must-Perform” Operations
A computer must have instructions capable of
performing four types of operations:

1. Data transfers between the memory and the

processor registers.

2. Arithmetic and logic operations on data.

3. Program sequencing and control.

4. I/O transfers
 Register Transfer Notation
 Identify a location by a symbolic name standing
for its hardware binary address (LOC, R0,…)

 Contents of a location are denoted by placing

square brackets around the name of the
location (R1←[LOC], R3 ←[R1]+[R2])

 Register Transfer Notation (RTN)

Assembly Language Notation

 Represent machine instructions and

programs.

 Move LOC, R1 means R1←[LOC]

 Add R1, R2, R3 means R3 ←[R1]+[R2]

 Instruction Formats
 Three-Address Instructions
 ADD R1, R2, R3
 Two-Address Instructions
 ADD R1, R2
 One-Address Instructions
 ADD M
 Zero-Address Instructions
 ADD
 RISC Instructions
 Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

Instruction Formats

Example: Evaluate (A+B)  (C+D)

 Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1  R2
Instruction Formats
Example: Evaluate (A+B)  (C+D)
 Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1  R2
6. MOV X, R1 ; M[X] ← R1
Instruction Formats
Example: Evaluate (A+B)  (C+D)
 One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORET ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STOREX ; M[X] ← AC
 Instruction Formats
Example: Evaluate (A+B)  (C+D)
 Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ←
(C+D)(A+B)
8. POP X ; M[X] ← TOS
Instruction Formats
Example: Evaluate (A+B)  (C+D)
 RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1  R3
8. STOREX, R1 ; M[X] ← R1
Using Registers
 Registers are faster
 Shorter instructions
 Potential speedup
 Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.
 Instruction Execution and
Straight-Line Sequencing
Address Contents

i
Assumptions:
Begin execution here Move A,R0
i+4
3-instruction
program
- One memory operand
Add B,R0
segment per instruction
i+8 Move R0,C
- 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word instruction
B Data for
the program
Two-phase procedure
-Instruction fetch
-Instruction execute
C
Page 43

Figure 2.8. A program for C  [A] + [B].

 i Move NUM1,R0
i+4 Add NUM2,R0

Branching i+8 Add NUM3,R0

•
•
•
i + 4n - 4 Add NUMn,R0
i + 4n Move R0,SUM

•
•
•
SUM
NUM1
NUM2

•
•
•
NUMn

Figure 2.9. A straight-line program for adding n numbers.

 Move N,R1
Clear R0

Branching LOOP
Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target
Move R0,SUM

Conditional branch
•
•
•
SUM
N n
NUM1

Figure 2.10. Using a loop to add n numbers. NUM2

•
•
•
NUMn
Condition Codes
Condition code / flags
Condition code register / status register
 N (negative)

 Z (zero)

 V (overflow)

 C (carry)

 Different instructions affect different flags

Conditional Branch Instructions

 Example: A: 11110000

 A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
 B: 0 0 0 1 0 1 0 0 11011100

C=1 Z=0
S=1
V=0
Status Bits

Cn-1
A B

Cn ALU
F
V Z S C
Fn-1

Zero Check
Addressing Modes
1. Register Addressing
2. Direct (Absolute) Addressing

3. Immediate Addressing

4. Indirect Addressing

5. Index Addressing

6. Relative Addressing

7. Auto Increment Addressing

8. Auto Decrement Addressing

Generating Memory Addresses
 How to specify the address of branch target?
 Can we give the memory operand address
directly in a single Add instruction in the loop?
 Use a register to hold the address of NUM1;
then increment by 4 on each pass through
the loop.
Addressing Modes

Opcode Mode ...

 Implied
 AC is implied in “ADD M[AR]” in “One-Address”
instr.
 TOS is implied in “ADD” in “Zero-Address” instr.
 Immediate
 The use of a constant in “MOV R1, 5”, i.e. R1 ←
5
 Register
 Indicate which register holds the operand
Addressing Modes
 Register Indirect
 Indicate the register that holds the number of the
register that holds the operand R1
MOV R1, (R2)
R2 = 3
 Autoincrement / Autodecrement
 Access & update in 1 instr. R3 = 5

 Direct Address
 Use the given address to access a memory
location
Addressing Modes
 Indirect Address
 Indicate the memory location that holds the
address of the memory location that holds the
data
AR = 101

100
101 0 1 0 4
102
103
104 1 1 0 A
Addressing Modes

 Relative Address
0
 EA = PC + Relative Addr 1
PC = 2 2

100
AR = 100
101
102 1 1 0 A
Could be Positive or 103
Negative 104
(2’s Complement)
 Addressing Modes
 Indexed
 EA = Index Register + Relative Addr

Useful with XR = 2
“Autoincrement” or
“Autodecrement”
+

100
AR = 100
101
Could be Positive or
Negative 102 1 1 0 A
(2’s Complement) 103
104
 Addressing Modes
 Base Register
 EA = Base Register + Relative Addr

Could be Positive or AR = 2
Negative
(2’s Complement)
+

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points to 103 0 1 0 7
the beginning of 104 0 0 5 9
an array
 Addressing Modes
Name Assembler syntax Addressingfunction
 The different
ways in which Immediate #Value Op erand = Value
the location of
an operand is Register Ri EA = Ri
specified in Absolute (Direct) LOC EA = LOC
an instruction
are referred Indirect (Ri ) EA = [Ri ]
to as (LOC) EA = [LOC]
addressing
modes. Index X(R i) EA = [Ri ] + X

Basewith index (Ri ,Rj ) EA = [Ri ] + [Rj ]

Basewith index X(R i,Rj ) EA = [Ri ] + [Rj ] + X
and offset

Relative X(PC) EA = [PC] + X

Autoincrement (Ri )+ EA = [Ri ] ;

Increment Ri

Autodecrement  (Ri ) Decrement R i ;

EA = [Ri]
Indexing and Arrays
 Index mode – the effective address of the operand
is generated by adding a constant value to the
contents of a register.
 Index register
 X(Ri): EA = X + [Ri]
 The constant X may be given either as an explicit
number or as a symbolic name representing a
numerical value.
 If X is shorter than a word, sign-extension is needed.
Indexing and Arrays
 In general, the Index mode facilitates access
to an operand whose location is defined
relative to a reference point within the data
structure in which the operand appears.
 Several variations:
(Ri, Rj): EA = [Ri] + [Rj]
X(Ri, Rj): EA = X + [Ri] + [Rj]
Relative Addressing
 Relative mode – the effective address is determined
by the Index mode using the program counter in
place of the general-purpose register.
 X(PC) – note that X is a signed number
 Branch>0 LOOP
 This location is computed by specifying it as an
offset from the current value of PC.
 Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.
Additional Modes
 Autoincrement mode – the effective address of the operand is
the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
 (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
 Autodecrement mode: -(Ri) – decrement first
Move N,R1
Move #NUM1,R2 Initialization
Clear R0
LOOP Add (R2)+,R0
Decrement R1
Branch>0 LOOP
Move R0,SUM

Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.
Assembly
Language
Types of Instructions
 Data Transfer Instructions
Name Mnemonic Data value is
Load LD not modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
 Data Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1
 Data Manipulation Instructions
Name Mnemonic
 Arithmetic Increment INC
Decrement DEC
 Logical & Bit Manipulation Add ADD
 Shift Subtract SUB
Multiply MUL
Divide DIV
Add with carry ADDC
Name Mnemonic Subtract with borrow SUBB
Clear CLR Negate NEG
Complement COM Name Mnemonic
AND AND Logical shift right SHR
OR OR Logical shift left SHL
Exclusive-OR XOR Arithmetic shift right SHRA
Clear carry CLRC Arithmetic shift left SHLA
Set carry SETC Rotate right ROR
Complement carry COMC Rotate left ROL
Enable interrupt EI Rotate right through carry RORC
Disable interrupt DI Rotate left through carry ROLC
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Subtract A – B but
Call CALL don’t store the result

Return RET
Compare
CMP
(Subtract) 10110001
Test (AND) TST
00001000

Mask
00000000
Conditional Branch
Instructions

Mnemonic Branch Condition Tested Condition

BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
 Basic
Input/Output
Operations
I/O
 The data on which the instructions operate
are not necessarily already stored in memory.
 Data need to be transferred between
processor and outside world (disk, keyboard,
etc.)
 I/O operations are essential, the way they are
performed can have a significant effect on the
performance of the computer.
Program-Controlled I/O
Example
 Read in character input from a keyboard and
produce character output on a display screen.
 Rate of data transfer (keyboard, display, processor)
 Difference in speed between processor and I/O device
creates the need for mechanisms to synchronize the
transfer of data.
 A solution: on output, the processor sends the first
character and then waits for a signal from the display
that the character has been received. It then sends the
second character. Input is sent from the keyboard in a
similar way.
 Bus

Program-Controlled I/O
Processor
DATAIN

SIN

Key board

Figure 2.19 Bus connection for processor

DATAOUT

SOUT

Display

, keyboard, and display

.

Example

- Registers
- Flags
- Device interface
Program-Controlled I/O
Example
 Machine instructions that can check the state
of the status flags and transfer data:
READWAIT Branch to READWAIT if SIN = 0
Input from DATAIN to R1

WRITEWAIT Branch to WRITEWAIT if SOUT = 0

Output from R1 to DATAOUT
Program-Controlled I/O
Example
 Memory-Mapped I/O – some memory
address values are used to refer to peripheral
device buffer registers. No special
instructions are needed. Also use device
status registers.
READWAIT Testbit #3, INSTATUS
Branch=0 READWAIT
MoveByte DATAIN, R1

WRITEWAIT Testbit #3, OUTSTATUS

Branch=0 WRITEWAIT
MoveByte R1, DATAOUT

Note: DATAIN and DATAOUT are addresses

 Program-Controlled I/O
Example

 Assumption – the initial state of SIN is 0 and the

initial state of SOUT is 1.

 Any drawback of this mechanism in terms of

efficiency?

 Alternate solution?

 Interrupt
Stacks and Queues
 0
.
.
.
.
TOP 0
1
SP 2 34
3 45 STACK
4 67
5 34
BOTTOM 6 95
.
.
.
2K-1
If word size is 32bit and stack memory is word sized

 PUSH
SUBSTRACT #4, SP
MOVE NEWITEM, (SP)
 POP
MOVE (SP), ITEM
ADD #4, SP

Textbook follows
 Additional
Instructions
Logical Shifts
 Logical shift – shifting left (LShiftL) and shifting right
(LShiftR)
C R0 0

before: 0 0 1 1 1 0 . . . 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 0

(a) Logical shift left LShiftL #2,R0

0 R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 0 0 0 1 1 1 0 . . . 0 1

(b) Logical shift irght LShiftR #2,R0

Arithmetic Shifts

R0 C

before: 1 0 0 1 1 . . . 0 1 0 0

after: 1 1 1 0 0 1 1 . . . 0 1

(c) Arithmetic shift right AShiftR #2,R0

 C R0

before: 0 0 1 1 1 0 . . . 0 1 1

Rotate after: 1 1 1 0 . . . 0 1 1 0 1

(a) Rotate left without carr

y RotateL #2,R0

C R0

before: 0 0 1 1 1 0 . . . 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 0

(b) Rotate left with carr

y RotateLC #2,R0

R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 1 1 0 1 1 1 0 . . . 0 1

(c) Rotate ight

r without carry RotateR #2,R0

R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 1 0 0 1 1 1 0 . . . 0 1

(d) Rotate irght with carry RotateRC #2,R0

Figure 2.32. Rotate instructions.

Multiplication and Division
 Not very popular (especially division)
 Multiply Ri, Rj
Rj ← [Ri] х [Rj]
 2n-bit product case: high-order half in R(j+1)
 Divide Ri, Rj
Rj ← [Ri] / [Rj]
Quotient is in Rj, remainder may be placed in R(j+1)
Encoding of
Machine
Instructions
Encoding of Machine
Instructions
 Assembly language program needs to be converted into machine
instructions. (ADD = 0100 in ARM instruction set)
 In the previous section, an assumption was made that all
instructions are one word in length.
 OP code: the type of operation to be performed and the type of
operands used may be specified using an encoded binary pattern
 Suppose 32-bit word length, 8-bit OP code (how many instructions
can we have?), 16 registers in total (how many bits?), 3-bit
addressing mode indicator.
 Add R1, R2 8 7 7 10
 Move 24(R0), R5
OP code Source Dest Other info
 LshiftR #2, R0
 Move #$3A, R1
 Branch>0 LOOP (a) One-word instruction
Encoding of Machine
Instructions
 What happens if we want to specify a memory
operand using the Absolute addressing mode?
 Move R2, LOC
 14-bit for LOC – insufficient
 Solution – use two words

OP code Source Dest Other info

Memory address/Immediate operand

(b) Two-word instruction

Encoding of Machine
Instructions
 Then what if an instruction in which two operands
can be specified using the Absolute addressing
mode?
 Move LOC1, LOC2
 Solution – use two additional words
 This approach results in instructions of variable
length. Complex instructions can be implemented,
closely resembling operations in high-level
programming languages – Complex Instruction Set
Computer (CISC)
Encoding of Machine
Instructions
 If we insist that all instructions must fit into a single
32-bit word, it is not possible to provide a 32-bit
address or a 32-bit immediate operand within the
instruction.
 It is still possible to define a highly functional
instruction set, which makes extensive use of the
processor registers.
 Add R1, R2 ----- yes
 Add LOC, R2 ----- no
 Add (R3), R2 ----- yes