Introduction to Hardware
Description Language
Rionel Belen Caldo, BSCpE, MPA, MSc ECE
Problem with Digital Circuit
Implementation
Imagine yourself
implementing the given
circuit on a printed circuit
board
Possible reactions:
1. Large circuit /PCB size will be
needed
2. Too much wiring / “spaghetti
of wires”
3. Time consuming
Our Wish
1. A small size circuit
2. No wiring among components
3. Easier to debug
4. Only one (1) substrate for the
physical implementation
Solution: Digital Programmable
Integrated Circuit
• Programmable Logic Arrays (PLA)
• Programmable Array Logic (PAL)
• Limitations:
1. Only for purely
combinational logic circuit
2. Sequential Operations are not possible
Solution: Digital Programmable
Integrated Circuit
Field Programmable Gate Array (FPGA)
FPGA Development Board
How to program the FPGA
• One way is to wire a digital schematic
circuit
• Eventually, download the design onto
the FPGA
How to Program the FPGA
Disadvantages of Schematic
Design Approach
1. Time consuming
2. Difficult to debug errors found
in simulation
3. Digging through a “spaghetti of
wires” to look for faults requires a
lot of patience
4. Large designs means large
circuit size to deal with
5. Likely to be suited only for ECEs
How to Program the FPGA
A Better way to program the FPGA is to use the HDL
approach
HDL- Hardware Description Language
A code similar to writing a code in C is used to describe
the behavior of a digital hardware circuit.
The code will be processed by a software tool known
as synthesis to convert it to a hardware equivalence
based on a target library.
A Sample HDL Code
module counter( clk, reset, cntout);
input clk;
input reset;
output [3:0] cntout;
reg[3:0] cntout;
always@(posedge clk or negedge reset)
begin
if (reset == 1'b0)
cntout <= 4'b0000;
else
cntout <= cntout + 4'b0001;
end
endmodule
Synthesis of the HDL Code
Implementation
Synthesis Tool
• Synthesis converts the HDL code to a hardware equivalence
using a specified Library
• Target Library can be
• standard Cell –for mask production or
• FPGA for design verification
• A code that passes syntax check does not guarantee
synthesizability
• When writing the code, designer should be conscious of the
hardware implementation rather than a software solution
Advantage of using HDL
• The code is human readable
• The code can merely represent the behavior of the
intended project (you don’t necessarily have to think
gate level)
• Debugging is a lot easier than having to sift through a
spaghetti of wires
• Converting the code to circuit is easy and fast. (Note:
this depends on the user’s ability to write the code
properly)
Popular HDL
•Verilog
•VHDL
•System C
Learning Verilog
• Verilog- Adopted by the Japanese companies. Chosen
by others due to its simpler structure.
• Studying Verilog is in one way similar to studying a
programming language
• It is therefore advisable that students pursuing HDL
course must already have some background in
computer language programming.
• However, while writing the model as if writing a
program, one should be conscious of the target
HARDWARE model, he is actually aiming at.
Verilog Reserve Words
[[Link] ]
Verilog Reserve Words
Verilog is case sensitive
Two types of Verilog Statements
Statements in Verilog are classified as either:
•Concurrent
Concurrent statements do not follow any order. Even when
the statements are jumbled up in order of appearance,
simulation results will remain the same.
•Sequential
Sequential statements are similar to statements written in
c language. When the order of the statements is changed,
the simulation result may also change.
Concurrent vs Sequential
NOTE: concurrent statements and sequential statements in
Verilog are grouped separately inside the architectural
body
•In many cases, concurrent statements are used for
combinational logic circuit modeling while sequential
statements are used for sequential circuit modeling.
•Sequential statements can also be used for combinational
circuit modeling.
Parts of a Verilog Code
•Module Header
•Port Declaration
•Variable /Wire
Declaration
•Main Body
Module Header
The main interface ports of the
hardware model are written in this
section.
Example:
module ha ( a, b, s, c);
Port Declaration
input a, b;
output s, c;
Variable / Wire Declaration
wire c1, c2, c3;
Reg[3:0] A;
Sample Model
module fulladd(a,b,c,s,cout);
Module
input a, b, c; Header
output s, cout;
Port List
wire s1, c1, c2;
assign s1 = a ^ b; Wire/Variable
assign c1 = a & b;
assign s = s1 ^ c;
assign c2 = s1 & c; Body
assign cout = c1 | c2;
endmodule
Verilog Syntax
signal Assignment Statement
This is used in concurrent area.
e.g. assign c = b;
As a general rule:
assign output or inout = input or inout
Logical Operators
Arithmetic Operators
Relational Operators
>, < , = , != , >=,
<=
Drill Problems
It’s time to work
on some drill
problems next
meeting
1 Corinthians 15:57 “But thanks be to God!
He gives us the victory through our Lord
Jesus Christ.
Colossians 3:17 “Whatever you do or say, do
it as a representative of the Lord Jesus,
giving thanks through him to God the
Father.”
Your goal is to work in such a way that
you are a good representative of Jesus
END of Presentation…
