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William Stallings Computer Organization and Architecture 8 Edition

This document provides an overview of key concepts related to computer organization and architecture, including: 1. The basic components of a computer system including the central processing unit (CPU), memory, and input/output modules. 2. How instructions are fetched from memory and executed by the CPU in sequential order through an instruction cycle and fetch-execute process. 3. Additional concepts like interrupts, buses, and bus arbitration that facilitate communication and data transfer between computer components.

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113 views

William Stallings Computer Organization and Architecture 8 Edition

This document provides an overview of key concepts related to computer organization and architecture, including: 1. The basic components of a computer system including the central processing unit (CPU), memory, and input/output modules. 2. How instructions are fetched from memory and executed by the CPU in sequential order through an instruction cycle and fetch-execute process. 3. Additional concepts like interrupts, buses, and bus arbitration that facilitate communication and data transfer between computer components.

Uploaded by

abbas
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© © All Rights Reserved
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Download as PPT, PDF, TXT or read online on Scribd
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William Stallings

Computer Organization
and Architecture
8th Edition

Chapter 3
Computer Functions and
Interconnection
von Neumann architecture and is based
on three key concepts:
• Data and instructions are stored in a
single read–write memory.
• The contents of this memory are
addressable by location, without regard to
the type of data contained there.
• Execution occurs in a sequential fashion
(unless explicitly modified) from one
instruction to the next.
Program Concept
• Hardwired systems are inflexible
• General purpose hardware can do
different tasks, given correct control
signals
• Instead of re-wiring, supply a new set of
control signals
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals are needed
• Also need temp storage (memory) and
way to get input and output
CPU exchanges data with memory
• A memory address register (MAR),
specifies the address in memory for the
next read or write
• Memory buffer register (MBR), contains
the data to be written into memory or
receives the data read from memory.
• Similarly, an I/O address register (I/OAR)
specifies a particular I/O device.
• An I/O buffer (I/OBR) register is used for
the exchange of data between an I/O
module and the CPU.
Memory
• A memory module consists of a set of
locations, defined by sequentially
numbered addresses.
• Each location contains a binary number
that can be interpreted as either an
instruction or data.
• An I/O module transfers data from
external devices to CPU and memory, and
vice versa.
• It contains internal buffers for temporarily
holding these data until they can be sent
on.
Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals

• We have a computer!
Components
• The basic function performed by a computer is
execution of a program, which consists of a set
of instructions stored in memory.
• The Control Unit and the Arithmetic and Logic
Unit constitute the Central Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is needed
—Main memory
Computer Components:
Top Level View
Instruction Cycle
• Two steps: Program execution halts only if the
—Fetch machine is turned off, some sort of
—Execute unrecoverable error occurs, or a
program instruction that halts the
computer is encountered
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
—e.g. jump
• Combination of above
Instruction Cycle State Diagram
Instruction Cycle State Diagram
• Instruction address calculation (iac):
Determine the address of the next instruction to be
executed. Usually, this involves adding a fixed number to
the address of the previous instruction.

• Instruction fetch (if): Read instruction from its


memory location into the processor.

• Instruction operation decoding (iod): Analyze


instruction to determine type of operation to be performed
and operand(s) to be used.
Instruction Cycle State Diagram
• Operand address calculation (oac): If the operation
involves reference to an operand in memory or available
via I/O, then determine the address of the operand.

• Operand fetch (of): Fetch the operand from memory or


read it in from I/O.

• Data operation (do): Perform the operation indicated in


the instruction.

• Operand store (os): Write the result into memory or out


to I/O.
Classes of Interrupts
• Mechanism by which other modules (e.g.
I/O) may suspend/stop normal
sequence of processing
• Program: Generated by some condition
that occurs as a result of an instruction
execution, such as arithmetic overflow,
division by zero, attempt to execute an
illegal machine instruction, or reference
outside a user’s allowed memory space.
Classes of Interrupts
• Timer: Generated by a timer within the
processor. This allows the operating
system to perform certain functions on a
regular basis.Used in pre-emptive multi-
tasking
• I/O:Generated by an I/O controller, to
signal normal completion of an operation
or to signal a variety of error conditions.
• Hardware failure:Generated by a failure
such as power failure or memory parity
error
Interrupt (simple concept)

Internal interrupts, or "software interrupts," are triggered by a software


instruction and operate similarly to a jump or branch instruction

An external interrupt, or a "hardware interrupt," is caused by an external


hardware module. As an example, many computer systems use interrupt driven
I/O, a process where pressing a key on the keyboard or clicking a button on the
mouse triggers an interrupt. The processor stops what it is doing, it reads the input
from the keyboard or mouse, and then it returns to the current program.
Software Interrupts
• Software interrupts are not really
interrupts at all.

• A software interrupt is a machine


instruction that causes a transfer of
control through the same mechanism
used by true interrupts
Transfer of Control via Interrupts
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts while
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Connecting
• All the units must be connected
• Different type of connection for different
type of unit
—Memory
—Input/Output
—CPU
Computer Modules
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write
—Timing
Input/Output Connection(1)
• Similar to memory from computer’s
viewpoint
• Output
—Receive data from computer
—Send data to peripheral
• Input
—Receive data from peripheral
—Send data to computer
Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
—e.g. spin disk
• Receive addresses from computer
—e.g. port number to identify peripheral
• Send interrupt signals (control)
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
Buses
• There are a number of possible
interconnection systems
• Single and multiple BUS structures are
most common
• e.g. Control/Address/Data bus
• e.g. Unibus
What is a Bus?
• A communication pathway connecting two
or more devices
• Usually broadcast
• Often grouped
—A number of channels in one bus
—e.g. 32 bit data bus is 32 separate single bit
channels
• Power lines may not be shown
Data Bus
• Carries data
—Remember that there is no difference between
“data” and “instruction” at this level
• Width is a key determinant of
performance
—8, 16, 32, 64 bit
Address bus
• Identify the source or destination of data
• e.g. CPU needs to read an instruction
(data) from a given location in memory
• Bus width determines maximum memory
capacity of system
Control Bus
• Control and timing information
—Memory read/write signal
—Interrupt request
—Clock signals
Bus Interconnection Scheme
Big and Yellow?
• What do buses look like?
—Parallel lines on circuit boards
—Ribbon cables
—Strip connectors on mother boards
– e.g. PCI (Peripheral Component Interconnect)
—Sets of wires
Physical Realization of Bus Architecture
Single Bus Problems
• Lots of devices on one bus leads to:
—Propagation delays
– Long data paths mean that co-ordination of bus use
can adversely affect performance
• Most systems use multiple buses to
overcome these problems
Traditional Bus Architecture
High Performance Bus
Bus Types
• Dedicated
—Separate data & address lines
• Multiplexed
—Shared lines
—Address valid or data valid control line
—Advantage - fewer lines
—Disadvantages
– More complex control
– Ultimate performance
Bus Arbitration
• More than one module controlling the bus
• e.g. CPU and DMA controller
• Only one module may control bus at one
time
• Arbitration may be centralised or
distributed
Centralised or Distributed Arbitration
• Centralised
—Single hardware device controlling bus access
– Bus Controller
– Arbiter
—May be part of CPU or separate
• Distributed
—Each module may claim the bus
—Control logic on all modules
Timing
• Co-ordination of events on bus
• Synchronous
—Events determined by clock signals
—Control Bus includes clock line
—A single 1-0 is a bus cycle
—All devices can read clock line
—Usually sync on leading edge
—Usually a single cycle for an event
Synchronous Timing Diagram
Foreground Reading
• Stallings, chapter 3
• 3.1,3.2,3.3,3.4
• www.pcguide.com/ref/mbsys/buses/

• In fact, read the whole site!


• www.pcguide.com/

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