B.

TECH PROJECT TITLE DEFEND SEMINAR 2019-20

FPGA Implementation of Digital Alarm

National Institute of Science & Technology

Clock Using Verilog HDL

Project ID:17142

By
Kumar Prateek ECE 201610744
Ravi Ranjan Kumar ECE 201610357

Under the guidance of

Prof. Mitu Baral
Co-advisor name: Prof. Manoj Kumar Senapati

Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [1]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Content
National Institute of Science & Technology

 Introduction

 Aim of the project

 Methodology

 Software/Hardware used

 List of features implemented

 Possible Outcome

 Reference

Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [2]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Introduction
National Institute of Science & Technology

 The process of measuring time has progressively become more accurate,

and the devices more localized ever since. In our modern time, the time is
predominately measured by mechanical, and recently by electronic clocks.

 Historically, clocks and watches of all sorts lie at an important crossroads

of science, technology and society. Changes in timekeeping technology
have influenced the character of scientific observation, aided the
development of other machine technologies and brought significant
revisions in the way people think about and behave in time.

 In this project, the more accurate clock using FPGA is presented.

Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [3]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Aim of the Project

National Institute of Science & Technology

 It is a time keeping digital alarm clock that displays time in hours and
minutes. The goal of this design is to implement all of the basic features
that one would normally expect to find on a standard digital alarm clock.

 Features such as standard twelve-hour time, clock/alarm setting

functionality, an alarm snooze feature, and an alarm alert indicator.

 The aim this project is to implement the functionality of a digital alarm

clock on a FPGA. As soon as the FPGA is switched on, the clock starts.

 The alarm can be set using the dip-switches provided on the FPGA board.
This is indicated through the LEDs of the corresponding dip switch. The
counter keeps rolling and as soon as the alarm goes off, a buzzer like sound
is magnified via a speaker.

Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [4]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Methodology
National Institute of Science & Technology

 The FPGA is mapped using the Verilog HDL.

 Firstly board mounted clock oscillator was divided to get the clock signal
that occurs every minute.

 The counter process is driven by the signal that occurs every sixty second.

 In this project four variable seg3 to seg0(MSB to LSB) are taken.

 At every one seconds seg0 is incremented ,when the value of seg0 reaches
9 it makes seg1 to increment by 1 and reset its own value to zero and
accordingly all the seg are incremented as per time.

 When the alarm match take place a variable starts toggling at desired
frequency for sound output speaker is used.
Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [5]
 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Software/Hardware used
National Institute of Science & Technology

HDL: Verilog
HDL Simulator: Xilinx ISE/ Vivado
FPGA : Spatran6
LCD Module(16*2 Alphanumeric)

Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [6]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

List of features implemented

National Institute of Science & Technology

 Time(12 hour format)

 Clock Setting functionality

 Alarm time setting functionality

 Alarm indicating Sound output

 Snooze function

Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [7]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Possible Outcome
National Institute of Science & Technology

The alarm clock worked as planned. All the important aspects of a good alarm
clock – its timing accuracy, functionality, ease of use, etc are all represented in
the final
prototype. The LCD alarm clock even feature a user-friendly menu system for
time
changes. In short, all the goals set during the planning of this project were
met. The only difficulty in the project occurred when the manufacturer’s
initialization sequence failed to work. This was fixed by using another
algorithm provided by internet resources.

Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [8]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Reference
National Institute of Science & Technology

 Burian, Christopher J. “LCD Technical FAQ”,

http://www.repairfaq.org/filipg/LINK/F_Tech_LCD.html, 1996

 “LCD (programming & pinouts)”,

http://www.repairfaq.org/filipg/LINK/F_LCD_progr.html, 1996

Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [9]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20
National Institute of Science & Technology

Kumar Prateek (ECE201610357) & Ravi Ranjan Kumar (ECE201610357 ) [10]