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Timing Diagram

1. The document discusses the timing diagrams of the 8085 microprocessor. Timing diagrams show the signal conditions and timing of operations graphically. They represent the execution time of instructions in terms of T-states. 2. The 8085 has 5 basic machine cycles - opcode fetch, memory read, memory write, I/O read, and I/O write. Timing diagrams are shown for sample instructions like STA 526AH, INR M, and MVI B, 43H to illustrate the machine cycles. 3. The timing diagrams are useful for understanding how the 8085 interfaces with memory and I/O devices by matching signal timings.

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506 views15 pages

Timing Diagram

1. The document discusses the timing diagrams of the 8085 microprocessor. Timing diagrams show the signal conditions and timing of operations graphically. They represent the execution time of instructions in terms of T-states. 2. The 8085 has 5 basic machine cycles - opcode fetch, memory read, memory write, I/O read, and I/O write. Timing diagrams are shown for sample instructions like STA 526AH, INR M, and MVI B, 43H to illustrate the machine cycles. 3. The timing diagrams are useful for understanding how the 8085 interfaces with memory and I/O devices by matching signal timings.

Uploaded by

KUMARASWAMY A MEC
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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UNIT-II 8085 MICROPROCESSOR AND 8051 MICROCONTROLLER 10

1. Introduction

2. Architecture of 8085

3. Pin Configuration

4. Addressing Modes

5. Instruction set – I

6. Instruction set – II

7. Instruction set - III

8. Timing diagram of 8085

9. Concepts of 8051 microcontroller

10. Block diagram.


A.Kumaraswamy AP/ME

Timing Diagram of 8085

 A graphical representation - provides information about the various conditions of signals


such as high/low, when a machine cycle is being executed.
 The peripheral devices includes memories, ports etc. be matched with microprocessors
with the help of timing diagram.
 It represents the execution time taken by each instruction in a graphical format.
 The execution time is represented in T - states.

Instruction Cycle: The time required to execute an instruction is called instruction cycle.

Machine Cycle: The time required to access the memory or input / output devices is
called machine cycle.
A.Kumaraswamy AP/ME

T - State
 The machine cycle and instruction cycle takes multiple clock periods.
 A portion of an operation carried out in one system clock period is called as T-state.

Machine cycles of 8085

The 8085 microprocessor has 5 basic machine cycles. They are

1. Opcode fetch cycle (4T)

2. Memory read cycle (3T)

3. Memory write cycle (3T)

4. I/O read cycle (3T)

5. I/O write cycle (3T)

Time period, T = 1/ f; where f = Internal clock frequency


A.Kumaraswamy AP/ME

Machine Cycle and State:


 The necessary steps carried out to perform the operation of accessing either memory or I/O
device constitute a machine cycle.
 In other words necessary steps carried out to perform a fetch, a read or a write operation
constitute a machine cycle.
A.Kumaraswamy AP/ME

1. Opcode fetch machine cycle of 8085 :


 Each instruction of the processor has one byte opcode.
 The opcodes are stored in memory, the processor executes the opcode fetch machine
cycle to fetch the opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
 The time taken by the processor to execute the opcode fetch cycle is 4T.
 In this time, the first, 3 T - states are used for fetching the opcode from memory and
the remaining T - states are used for internal operations by the processor.
1. Opcode fetch machine cycle of 8085 :
A.Kumaraswamy AP/ME
A.Kumaraswamy AP/ME

2. Memory Read Machine cycle of 8085

 The memory read machine cycle


is executed by the processor to
read a data byte from memory.
 The processor takes 3T states to
execute this cycle.
 The instructions which have more
than one byte word size will use
the machine cycle after the
opcode fetch machine cycle.
A.Kumaraswamy AP/ME

3. Memory Write Machine Cycle of 8085

 The memory write machine


cycle is executed by the
processor to write a data byte in
a memory location.
 The processor takes, 3T states to
execute this machine cycle.
A.Kumaraswamy AP/ME

4. I/O Read Cycle of 8085

 The I/O Read cycle is executed by


the processor to read a data byte
from I/O port or from the peripheral,
which is I/O, mapped in the system.
 The processor takes 3T states to
execute this machine cycle.
 The IN instruction uses this machine
cycle during the execution.
A.Kumaraswamy AP/ME

Timing Diagram for STA 526AH

 STA refers to Store Accumulator - The contents of the accumulator is stored in the
specified address (526A).
 The opcode of the STA instruction is said to be 32H. It is fetched from the memory
41FFH of machine cycle.
 Then the lower order memory address is read (6A) - Memory Read Machine Cycle
 Read the higher order memory address (52) - Memory Read Machine Cycle
 The combination of both the addresses are considered and the content from
accumulator is written in 526A - Memory Write Machine Cycle
 Assume the memory address for the instruction and let the content of accumulator is
C7H. So, C7H from accumulator is now stored in 526A.
Timing Diagram for STA 526AH
A.Kumaraswamy AP/ME
A.Kumaraswamy AP/ME

Timing Diagram for INR M

 Fetching the Opcode 34H from the memory 4105H (of cycle).
 Let the memory address (M) be 4250H. (MR cycle - to read Memory address and
data).
 Let the content of that memory is 12H.
 Increment the memory content from 12H to 13H. (MW machine cycle)
Timing Diagram for INR M
A.Kumaraswamy AP/ME
A.Kumaraswamy AP/ME

Timing Diagram for MVI B, 43H.

 Fetching the opcode


06H from the memory
2000H (of machine
cycle)
 Read (move) the data
43H from memory
2001H (memory read)
A.Kumaraswamy AP/ME

REFERENCES:

 Ramesh S Gaonkar, “Microprocessor Architecture, Programming, and


Applications with the 8085”, 5th Edition, Prentice Hall, 2008.

 Krishna Kant, “Microprocessors & Microcontrollers”, Prentice Hall of India,


2007.

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