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Assignment For Week9

The document contains 10 questions about concepts related to clock design and power optimization in integrated circuits. The questions cover topics such as clock skew, hold violations, clock tree design, power consumption calculations, crosstalk mitigation techniques, and RC circuits. Responses would require explaining these concepts and performing calculations related to power, resistance, capacitance, and circuit behavior.

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Ashok Chetan
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34 views2 pages

Assignment For Week9

The document contains 10 questions about concepts related to clock design and power optimization in integrated circuits. The questions cover topics such as clock skew, hold violations, clock tree design, power consumption calculations, crosstalk mitigation techniques, and RC circuits. Responses would require explaining these concepts and performing calculations related to power, resistance, capacitance, and circuit behavior.

Uploaded by

Ashok Chetan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Assignment questions:

1) Which of the following is not considered for hold uncertainty


(A) clock skew
(B) clock jitter
(C) Sign off margins
(D) Impact of IR drop
2) Explain how you fix hold violations. How do you make sure setup does-not degrade while fixing for hold.
3) Explain significance of the following
a) clock transition/slew
b) clock skew
c) clock latency/insertion delay
4) Given a scenario where clock latency is high, suggest any 2 methods for reducing clock latency
5) Why do we build a clock tree using limited number of cells. Explain the basis on which you would choose these cells
6) For the below given scenario, calculate average switching power consumption of the design
a) Total number of cells(all combinational) = 100K of which 10% are clock cells.
b) Input cap of clock cells = 2fF and for rest of the cells, input cap = 1fF
c) Frequency of operation of the design = 1.5GHz, clock cells switch twice in a cycle and rest of the logic switches
10% on an average
d) Total route length = 1000um. Assume 10% of it to be clock routing.
e) Copper is used for routing. Assume resistivity 0.02 ohm-micro-meter, Capacitance = 1fF/um for all wire
segments
f) Operating voltage for this calculation can be assumed to be 1.1V
7) Which of the following statements is true. Which of them is false
a) Resistance of copper wire is lower at 125C compared to what it is at 25C
b) Thinner wires have higher resistance
c) Given a design which dissipates 1W as leakage power running @ 1GHz, the leakage power dissipation reduces
to 500mW, once the frequency of operation is reduced to 500Mhz, keep all other things unchanged.
d) clock gaters are put in clock path to reduce average dynamic power consumption
8) Explain OCV. How does it impact your design timing
9) Explain in detail, various methods by which you mitigate the impact of crosstalk on clock nets.
10) In the below RC circuit, assume the capacitor is discharged to start with. Answer below questions
a) When the switch is closed at t=0, what is the initial current flowing through the 2 Kohm resistor at t=0+
b) At steady-state i.e., at t = infinity, what is the current flowing through the 500 ohm resistor

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