DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING

2017-18

Student Roll. no : 17104C2001, 17104C2003, 17104C2021, 17104C2052, 17104C2059 Faculty Incharge: Prof. Tejal Page

SRAM 6 TRANSISTORS READ OPERATION

Why use an SRAM? 6T SRAM Memory cell Diagram

There are many reasons to use an SRAM or a DRAM in a system design.
Design tradeoffs include density, speed, volatility, cost, and features. All
of these factors should be considered before selecting a RAM for the
system design.
Speed: 250 MHz and beyond, with access and cycle times equal to the
clock cycle used by the microprocessor.
Density: The largest SRAMs are expected to be only 16 Mb.
Volatility: SRAM cells do not need to be refreshed. They are available
for reading and writing all time.
Cost: A well-designed SRAM is an effective cost performance solution.
Custom Features: Features can be connected or disconnected according
to the requirements of the user.

SRAM Basic Architecture Basic Architecture

The basic architecture of a static RAM includes one or more
rectangular arrays of memory cells with support circuitry to
Add decode addresses, and implement the required read and write
operations. Additional support circuitry used to implement
special features, such as burst operation, may also be present
on the chip.

SRAM Memory Cell Layout

SRAM Memory Cell Layout (Packaging)

IBM Microelectronics' SRAMs come in three different packages
depending on their cost and performance. PC-compatible SRAMs are
usually sold in 52-pin PLCC or 100-pin TQFP packages. These
packages comply with the JEDEC standards for pinout and footprint.
Ultra-high performance SRAMs, including most of the SRAMs geared
to high-end workstations, require a higher performance package —
the 119-pin Ball Grid Array (BGA) package. The BGA package has
superior performance characteristics such as shorter leads from chip
to package and internal planes that result in lower inductance and 6T SRAM Cell Read Operation
reduced package-related noise. 1. Before the clock transition (low to high) that initiates the read operation
(1), the row and column addresses must be applied to the address input pins
(ADDR) (2), the chip must be selected (3), and the Write Enable must be high
(4).
6T SRAM Cell Read Operation Timing Diagram Note that each of these signals must be present and valid a specified
amount of time (the set up time) before the clock switches from low to high,
and must remain valid for a specified amount of time (the hold time) after
the clock switches (7). When the chip select (CS) is low, the chip is selected.
When it is high (inactive), the chip cannot accept any input signals. The
Write Enable is used to choose between reading and writing. When it is low,
a write operation occurs; when it is high, a read operation occurs.
2. On the rising edge of the clock (CLK) (1), the address is registered and the
read cycle begins.
3. If the Output Enable is being used to control the appearance of data at
the output, OE must go low (5). OE is an asynchronous signal; it can be
activated at any time. When OE is high, the DQs are tri-stated; data from the
memory will not appear on the outputs.
4. Data appears at the output pins of the SRAM (6). The time at which the
data appears depends on the access time of the device, the delay associated
with the Output Enable and the type of SRAM you are using. The access time
of the SRAM is the amount of time required to read a bit of data from the
memory when all of the timing requirements have been met.

Class: T.E. EXTC-C (1st Batch) Subject: Digital VLSI Design

References: http://www.chips.ibm.com