ASIC CONSTRUCTION,

PARTITIONING, FLOOR
PLANNING AND ROUTING
Prabhavathi P,
Associate Professor, Department of ECE, BNMIT
Outline
 Physical Design
 CAD Tools
 Methods and Algorithms
 Timing-driven floor-planning and placement
design flow
 System Partitioning
 Floor - planning
 Placement
 Routing
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 Physical design
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 The physical design of ASICs is normally divided into

system partitioning, floor - planning, placement, and
routing.
 A microelectronic system is the town and the ASICs
are the buildings.
 System partitioning corresponds to town planning.
 ASIC floor-planning is the architects job.
 Placement is done by the builder.
 Routing is done by the electrician.

 We shall design most, but not all, ASICs using these

design steps.
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 Physical Design
4

 The steps may be performed in a

slightly different order, iterated
or omitted depending on the type
and size of the system and its
ASICs.
 As the focus shifts from logic to
interconnect, floor – planning
assumes an important role.
 Each of the steps shown in the
figure must be performed and
each depends on previous step.
 However, the trend is toward
completing these steps in a
parallel fashion and iterating,
rather than in a sequential
manner.

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 We must first apply system partitioning to divide a microelectronics

system into separate ASICs.
 In floor-planning we estimate sizes and set the initial relative
locations of the various blocks in our ASIC
 At the same time we allocate space for clock and power wiring and
decide on the location of the I/O and power pads.
 Placement defines the location of the logic cells within the flexible
blocks and sets aside space for the interconnect to each logic cell.
 Placement for a gate-array or standard-cell design assigns each
logic cell to a position in a row.
 For an FPGA, placement chooses which of the fixed logic resources
on the chip are used for which logic cells.
 Floor-planning and placement are closely related and are sometimes
combined in a single CAD tool.

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 Routing makes the connections between logic cells.

 Routing is a hard problem by itself and is normally split into two distinct
steps, called global and local routing.
 Global routing determines where the interconnections between the placed
logic cells and blocks will be situated.
 Only the routes to be used by the interconnections are decided in this step,
not the actual locations of the interconnections within the wiring areas.
 Global routing is called loose routing for this reason.
 Local routing joins the logic cells with interconnections.
 Information on which interconnection areas to use comes from the global
router.
 Only at this stage of layout do we finally decide on the width, mask layer,
and exact location of the interconnections.
 Local routing is also known as detailed routing.

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 In order to develop a CAD tool it is necessary to

convert each of the physical design steps to a
problem with well-defined goals and objectives.
 The goals for each physical design step are the
things we must achieve.
 The objectives for each step are things we would
like to meet on the way to achieving the goals.
 Some examples of goals and objectives for each of
the ASIC physical design steps are as follows:
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 System partitioning:
 Goal: Partition a system into a number of ASICs.
 Objective: Minimize the number of external
connections between the ASICs, keep each ASIC
smaller than a maximum size.
 Floor-planning:
 Goal: Calculate the sizes of all the blocks and assign
them locations.
 Objective: Keep the highly connected blocks
physically close to each other.

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 Placement:
 Goal: Assign the interconnect areas and the location of
all the logic cells within the flexible blocks.
 Objective: Minimize the ASIC area and the
interconnect density.
 Global routing:
 Goal:Determine the location of all the interconnect.
 Objective: Minimize the total interconnect area used.

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 Detailed routing:
 Goal: Completely route all the interconnect on the
chip.
 Objective: Minimize the total interconnect length used.

 There is no magic recipe involved in the choice of

the ASIC physical design steps.
 Floor-planning and placement are often thought of
as one step and in some tools placement and
routing are performed together.

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 Methods and Algorithms
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 A CAD tool needs methods or algorithms to generate a solution to

each problem using a reasonable amount of computer time.
 Often there is no best solution possible to a particular problem, and
the tools must use heuristic algorithms, or rules of thumb, to try and
find a good solution.
 To solve each of the ASIC physical design steps we
 require:
 a set of goals and objectives, a way to measure the goals and objectives
 an algorithm or method to find a solution that meets the goals and
objectives
 The term algorithm is usually reserved for a method that always
gives a solution.

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 We need to know how practical any algorithm is.

 We say the complexity of an algorithm is O(f(n)).
 The function f (n) is usually one of the following kinds:
 f (n) = constant
 f (n) = log n
 f (n) = n
 f (n) = n log n
 f (n) = n 2
 As designers attempt to achieve a desired ASIC performance they make a
continuous trade-off between speed, area, power, and several other factors.
 Presently CAD tools are not smart enough to be able to do this alone.
 Current CAD tools are only capable of finding a solution subject to a few,
very simple, objectives.

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 Timing-driven floor-planning and
13
placement design flow
 The flow consists of the following steps:
 Design entry
 Synthesis

 Initial floor-plan

 Synthesis with load constraints

 Timing-driven placement

 Synthesis with in-place optimization

 Detailed placement

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 Design entry:
 The input is a logical description with no physical
information.
 Synthesis:
 The initial synthesis contains little or no information on any
interconnect loading.
 The output of the synthesis tool (EDIF net-list) is the input
to the floor-planner.
 Initial floor-plan:
 From the initial floor-plan inter-block capacitances are
input to the synthesis tool as load constraints and intra-
block capacitances are input as wire-load tables.

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 Synthesis with load constraints:

 At this point the synthesis tool is able to resynthesize the
logic based on estimates of the interconnect capacitance
each gate is driving.
 The synthesis tool produces a forward annotation file to
constrain path delays in the placement step.
 Timing-driven placement:
 After placement using constraints from the synthesis tool,
the location of every logic cell on the chip is fixed and
accurate estimates of interconnect delay can be passed back
to the synthesis tool.

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 Synthesis with in-place optimization (IPO):

 The synthesis tool changes the drive strength of gates
based on the accurate interconnect delay estimates
from the floor-planner without altering the netlist
structure.
 Detailed placement:
 The placement information is ready to be input to the
routing step.

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 System Partitioning
19

 Introduction
 Measuring Connectivity
 A Simple Partitioning Example
 Partitioning Methods
 Constructive Partitioning
 Iterative Partitioning Improvement
 The Kernighan Lin Algorithm
 The Fiduccia Mattheyses Algorithm
 The Ratio-Cut Algorithm
 The Look-ahead Algorithm
 Simulated Annealing

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 Introduction
20

 Microelectronic systems typically consist of many

functional blocks.
 If a functional block is too large to fit in one ASIC, we
may have to split, or partition, the function into pieces
using goals and objectives that we need to specify.
 We can use CAD tools to help us with this type of
system partitioning.
 System partitioning requires goals and objectives,
methods and algorithms to find solutions, and ways to
evaluate these solutions.
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 The levels of partitioning:

 Board
 Chip
 The goal of partitioning is to divide the part of the
system so that each partition is a single ASIC.
 To do this we may need to take into account any or all
of the following objectives:
 A maximum size for each ASIC
 A maximum number of ASICs
 A maximum number of connections for each ASIC
 A maximum number of total connections between all
ASICs
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 Measuring Connectivity
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 To measure connectivity we need some help from the

mathematics of graph theory.
 Figure (a) shows a circuit schematic, netlist, or network.
The network consists of circuit modules A-F.
 Equivalent terms for a circuit module are a cell, logic cell,
macro, or a block.
 A cell or logic cell usually refers to a small logic gate, but
can also be a collection of other cells.
 Macro refers to gate-array cells.
 Block is usually a collection of gates or cells.
 Each logic cell has electrical connections between the
terminals (connectors or pins).

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 A Simple partitioning example
29

 Figure 2 (a) shows a simple network we need to partition.

 There are 12 logic cells, labeled A-L, connected by 12 nets (labeled
1-12).
 At this level, each logic cell is a large circuit block and might be
RAM, ROM, an ALU, and so on.
 Each net might also be a bus, but, for the moment, we assume that
each net is a single connection and all nets are weighted equally.
 The goal is to partition our simple network into ASICs.
 Our objectives are the following:
 Use no more than three ASICs.
 Each ASIC is to contain no more than four logic cells.
 Use the minimum number of external connections for each ASIC.
 Use the minimum total number of external connections.

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 Partitioning methods
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 Two types of algorithms are used:

 Constructive partitioning
 Iterative partitioning improvement

 Constructive partitioning, which uses a set of rules to

find a solution.
 Iterative partitioning improvement (or iterative
partitioning refinement), which takes an existing
solution and tries to improve it.
 Often we apply iterative improvement to a constructive
partitioning.

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 Constructive partitioning
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 The most common constructive partitioning algorithms

use seed growth or cluster growth.
 A simple seed-growth algorithm for constructive
partitioning consists of the following steps:
 Start a new partition with a seed logic cell.
 Consider all the logic cells that are not yet in a partition.
Select each of these logic cells in turn.
 Calculate a gain function, g(m), that measures the benefit of
adding logic cell m to the current partition. One measure of
gain is the number of connections between logic cell m and
the current partition.

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 Add the logic cell with the highest gain g(m) to the current
partition.
 Repeat the process from step 2. If you reach the limit of
logic cells in a partition, start again at step 1.
 We may choose different gain functions according to
our objectives (but we have to be careful to distinguish
between connections and nets).
 The algorithm starts with the choice of a seed logic cell
(seed module, or just seed).
 The logic cell with the most nets is a good choice as
the seed logic cell.
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 We can also use a set of seed logic cells known as a

cluster or clique borrowed from graph theory
 A clique of a graph is a subset of nodes where each pair
of nodes is connected by an edge like your group of
friends at school where everyone knows everyone else
in your clique.
 In some tools you can use schematic pages (at the leaf
or lowest hierarchical level) as a starting point for
partitioning.
 If you use a high-level design language, you can use a
Verilog module or VHDL entity/architecture as seeds.
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 Iterative partitioning Improvement
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 The most common iterative improvement algorithms are

based on interchange and group migration.
 The process of interchanging (swapping) logic cells in an
effort to improve the partition is an interchange method.
 If the swap improves the partition, we accept the trial
interchange; otherwise we select a new set of logic cells to
swap.
 There is a limit to what we can achieve with a partitioning
algorithm based on simple interchange.
 For example, Figure (c) shows a partitioning of the network
of part a using a constructed partitioning algorithm with
logic cell C as the seed.

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 To get from the solution shown in part (c) to the solution of part (b),
which has a minimum number of external connections, requires a
complicated swap.
 The three pairs: D and F, J and K, C and L need to be swapped all at
the same time.
 It would take a very long time to consider all possible swaps of this
complexity.
 A simple interchange algorithm considers only one change and
rejects it immediately if it is not an improvement.
 Algorithms of this type are greedy algorithms in the sense that they
will accept a move only if it provides immediate benefit.
 Such short sightedness leads an algorithm to a local minimum from
which it cannot escape.

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 Group migration consists of swapping groups of logic cells

between partitions.
 The group migration algorithms are better than simple interchange
methods at improving a solution but are more complex.
 Almost all group migration methods are based on the powerful and
general Kernighan Lin algorithm (KL algorithm) that partitions a
graph.
 The problem of dividing a graph into two pieces, minimizing the
nets that are cut, is the min-cut problem a very important one in
VLSI design.
 The KL algorithm can be applied to many different problems in
ASIC design.
 We shall examine the algorithm next and then see how to apply it to
system partitioning.

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