DIGITAL ELECTRONIC

(DEE 2123)
Prepared By :
Rokiah Nasaruddin
Department of Electrical Engineering
Diploma Study Center
Universiti Tun Hussein Onn Malaysia
[email protected]

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 Chapter 6
Digital Arithmetic
• 6.1 Binary arithmetic • 6.10 Arithmetic circuit
• - addition • - half adder
• - subtraction • - full adder
• - multiplication • 6.11 Parallel adder
• - division • 6.12 Parallel adder with registers
• • 6.13 BCD adder circuit
6.2 Signed numbers • 6.14 Multiplier circuit
• - sign and magnitude
• - 1’s complement and 2’s
• complement
• 6.3 Addition using 2’s complement
• 6.4 Subtraction using 2’s complement
6.5 Multiplication
• 6.6 Division
6.7 BCD Arithmetic
• 6.8 Hexadecimal Arithmetic

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6.1.1 Binary Addition
• The four basic rules for
adding binary digits are: Example :

• 0 + 0 = 0 Sum of 0 with a carry of 0 110 6

• + 100 +4
0 + 1 = 1 Sum of 1 with a carry of 0 -------- ----
• 1 + 0 = 1 Sum of 1 with a carry of 0 1010 10
• 1 + 1 = 10 Sum of 0 with a carry of 1 -------- ----
• The first three rules result
in a single bit.
• In the fourth rule the
addition of two 1’s yields
a binary 2 (10).

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6.1.2 Binary Subtraction
• The four basic rules Example:
for subtraction are:
101 5
• 0-0 = 0 - 011 -3
• 1-1 = 0 ------ ----
010 2
• 1- 0 = 1 ------ ----
• 10-1 =1 (0-1 with a
borrow of 1)

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6.1.3 Binary Multiplication
• The four basic rules for Example 111 x 101
multiplication are:
111
• 0x0=0 x 101
• 0x1=0 -------------
111
• 1x0=0 000
+ 111
• 1x1=1 ------------
100011
------------
• Binary multiplication is
performed in the same
manner as with decimal
numbers
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6.1.4 Binary Division
• Division in binary • Example
follows the same
procedure as division _ 11
in decimal 10 ) 110 3
10 2) 6
------ 6
10 -----
10 0
-------
00

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6.2 Signed Numbers
• Digital systems must be able to handle both
positive and negative numbers. A signed
number consists of both sign and magnitude
information. The sign indicates whether a
number is positive or negative and the
magnitude is the value of the number. There are
three forms in which a signed integer can be
represented in binary :
• 1) sign-magnitude
• 2) 1’s complement
• 3) 2’s complement

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6.2.1 Sign-Magnitude Form
• When a signed binary number is represented in
sign-magnitude form , the left-most bit is the sign
bit, which tells you whether the number is
positive or negative.
• A 0 is for positive, and a 1 is for negative.
• The remaining bits to the right are the magnitude
bits.
• For example, the number +25 expressed as an 8
bit sign-magnitude binary number is 00011001.
The number -25 is 10011001.

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6.2.2 1’s Complement Form
• Positive number in 1’s complement form
are represented the same way as the
positive sign-magnitude numbers.
• Negative numbers are the complement of
the corresponding positive number.
• For example, using 8 bit binary number,
+25 is 00011001. However, -25 is
11100110.
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6.2.3 2’s Complement Form
• Positive numbers in 2’s complement form are
represented the same way as in the sign-
magnitude and 1’s complement form.
• Negative numbers are the 2’s complement of the
corresponding positive numbers. The positive
form is 1’s complemented and then added 1 to it.
• For example, the 2’ complement of +25 is
00011001. The 2’s complement of -25 is
11100111.

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6.2.4 The Decimal Value of Signed
Numbers
• Sign-magnitude:
The sign is determined by the sign bit. The
value is determined by summing the
weights in all the magnitude bit positions
where there are 1s.
Example : The decimal value of 10010101 is
– (1x24+1x22+1x20) = -21

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 1’s Complement

• For positive numbers the value is determined by

summing the weights in all bit positions where
there are 1’s.

• For negative numbers ( the msb is 1), 1’s

complement all the bits and sum up the weights
in all bit positions where there are 1’s.

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 2’s Complement
• For positive numbers the value is
determined by summing the weights in all
bit positions where there are 1’s.

• For negative numbers ( the msb is 1), 2’s

complement all the bits and sum up the
weights in all bit positions where there are
1’s.
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Table 6.1

Decimal 2’s Complement 1’s Complement Signed-magnitude

+7 0111 0111 0111

+6 0110 0110 0110
+5 0101 0101 0101
+4 0100 0100 0100
+3 0011 0011 0011
+2 0010 0010 0010
+1 0001 0001 0001
+0 0000 0000 0000
-0 - 1111 1000
-1 1111 1110 1001
-2 1110 1101 1010
-3 1101 1100 1011
-4 1100 1011 1100
-5 1011 1010 1101
-6 1010 1001 1110
-7 1001 1000 1111
-8 1000 -
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• Table 6.1 lists all possible 4-bit signed binary numbers in
the three representations. The equivalent decimal is also
shown for reference.
• The positive numbers for the three representations are
identical and have 0 in the leftmost position. The negative
numbers have a 1 in the leftmost bit position. The 1’s
complement and sign-magnitude form has a positive and a
negative 0.

• The sign-magnitude system is used in ordinary arithmetic,

but is awkward when employed in computer arithmetic. The
1’s complement imposes some difficulties in designing the
circuit and is seldom used. The 2’s complement method
results in simpler circuit and is exclusively employed in
computer arithmetic.

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 Range for Unsigned Numbers
• For unsigned numbers all the bits are used
to represent the values.
• For an 8 bit number, the range is between
• 00000000 to 11111111
• 0 to 255
• 0 to 2n -1 where n is the bit.

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 Range for signed numbers
• For signed numbers in the 2’s complement
form, the MSB is used for the sign.
• The range is from negative to positive. For
an 8 bit number it is between
• 10000000 (-128) to 01111111 (127).
• -(2n-1) to 2n -1 -1

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6.3 Addition Using 2’s Complement

• Examples:
The addition of two
• + 6 00000110
signed binary numbers • +13 00001101
with negative numbers • ------ -------------
• +19 00010011
represented in 2’s
complement form is •
obtained by adding the • •
+ 6 00000110
two numbers, including • -13 11110011
• ------ -------------
their sign bits. A carry out • -7 11111001
of the sign-bit position is
dicarded.

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• The negative • Examples
numbers must be in
•
the 2’s complement •
- 6
+13
11111010
00001101
form. • ------ -------------
• + 7 00000111
• If the sum obtain is
negative, it is in the
2’s complement form • - 6 11111010
• -13 11110011
• ------ -------------
• -19 11101101

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6.4 Binary Subtraction
• Take the 2’s complement of the
subtrahend and add it to the minuend. A
carryout of the sign-bit is discarded. The
subtraction operation is changed to an
addition operation.
• (±A) – (+B) = (±A) + (-B)
• (±A) – (-B) = (±A) + (+B)

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• Example:

• 01100100 01100100
• - 00110010 » + 11001110
• -------------- discard --------------
• 1 00110010

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6.5 Binary multiplication
In ordinary multiplication: mulitipliand

If the multiplier is 0, the • 0111 multiplier

partial product is 0. x 101
If the multiplier is 1, the --------
partial product is the 0111 partial products
000
multiplicand. Each partial + 0111
product is shifted to the ----------- product
left. Finally, all the partial 100011
products are total up.

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 6.6 BCD Addition
• For BCD addition, use the rules for binary
addition. However, if the result is > 1001 add
0110 to correct the result.
• Example : (2) 9 + 4= 13
(1) 86 +13= 99 1001
+ 0100
1000 0110 -------
0001 0011 1101 not BCD
-------------- + 0110 add 6
1001 1001 --------------
0001 0011

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6.8 Hexadecimal Addition
• Operation is as decimal addition, except
when the sum is ≥ 16, you then subtract
16 and carry 1.
Example

23 DF
+16 + A1
------ -------
39 180
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6.9 Hexadecimal Subtraction
• The common way to do this is to change the
negative number to binary, then do a 2’s
complement. Change back to hexadecimal and
add the numbers
• Example : 84 -2A
• 2A = 0010 1010
• -2A = 1101 0101+1 =11011010=D6
84
+ D6
------
discard 1 5A
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6.10 Arithmetic Circuit
• Addition. subtraction, multiplication and division
are among the functions performed by digital
computers. The most basic arithmetic operation
is the addition of 2 binary bits. A combinational
circuit that performs the addition of two bits is
called a half adder. One that performs the
addition of three bits (two significant bits and a
previous carry) is a full adder. The names of the
circuits stem from the fact that two half adders
can be combined to implement a full adder.
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6.10.1 Half Adder
• Truth Table

A B Sum Carry

0 0 0 0
0 1 1 0
1 0 1 0 Half Adder Circuit
1 1 0 1 Sum= A B

Carry = A.B

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6.10.2 Full Adder
Truth Table

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6.10.3 Full Adder Circuits
• Circuit derive from • Circuit built from two
logic equations half adders

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6.11 Parallel Adder
This digital circuit produces the arithmetic
sum of two binary numbers. It can be
constructed with full adders connected in
cascade, with the output carry from each
full adder connected to the input carry of
the next full adder in the chain. Figure
below shows the interconnection of four
full adder circuits to provide a 4-bit binary
ripple carry adder.
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6.11.1 4-bit Ripple Carry Adder

• The carry bit ripples from one stage to the next.

• This is a drawback since the carry information has to propagate
through all stages. This may lead to undesirably long delays before
the output stabilizes.

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6.12 Parallel Adder with registers

Load

Register A

4-bit full adder

Full Adder

output

Register B

clear
transfer

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 6.13 BCD Adder circuit
For numbers:
0-9
BCD number

4-bit adder

BCD number

4-bit adder Correction adder

BCD Sum

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• When the binary sum is ≤ 1001, the BCD
number is correct. When the binary sum is
>1001, we obtain a non valid BCD
number. The addition of 0110 to the binary
sum converts it to the correct BCD
representation, and also produce an
output carry as required.

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6.15 Parallel adder/subtractor
When Co = 0, the circuit is
an adder.
B 0 = B. The full adder
receives input B and the 4-bit full adder
carry in is 0
When Co = 1,B 1 = B’
The B inputs are all
complemented and a 1 is
added through the input
carry. The circuit
performs the operation A
plus the 2’s complement
of B.

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