Scribd
Upload
32 views

The FPGA Implementation of The Digital Receiver: Ceiec

The document discusses the FPGA implementation of a digital receiver. It describes: 1) Using a polyphase filter with N times decimation to reduce the data rate from the ADC input. 2) Employing an IP core to further decimate the data from 600MHz to 75MHz. 3) Recovering the data stream to its original order using column-to-row sorting after decimation. 4) Implementing the polyphase filter coefficients from Matlab and optimizing them for the FPGA.

Uploaded by

amanuel abreha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
32 views

The FPGA Implementation of The Digital Receiver: Ceiec

The document discusses the FPGA implementation of a digital receiver. It describes: 1) Using a polyphase filter with N times decimation to reduce the data rate from the ADC input. 2) Employing an IP core to further decimate the data from 600MHz to 75MHz. 3) Recovering the data stream to its original order using column-to-row sorting after decimation. 4) Implementing the polyphase filter coefficients from Matlab and optimizing them for the FPGA.

Uploaded by

amanuel abreha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 6

CEIEC

The FPGA implementation of the


digital receiver
FPGA implementation of the digital receiver CEIEC

Poly phase
 AD input N times Poly phase
decimation filter

PDW output
Parameter
code Detection

FPGA implementation of the poly-phase digital receiver


FPGA implementation of the digital receiver CEIEC

Poly phase
N times decimation
Still it is still large for the FPGA
The A/D output data could be 2 or 4 times decimated. to process  so use IP core to
ADC channels : Fs = 2.4 GHz  /4  600 MHz reduce its data rate

8 times decimation can be achieved when the data received by FPGA is


IP core Fs = 600 MHz  /8  75 MHz (=/32)
processed by the decimation IP core.
After the decimation, the data stream will be recovered to original one
The input data is written in column and the output data is read in rows
by order sorting .
FPGA implementation of the digital receiver CEIEC

Poly phase

 The coefficient of prototype filter is obtained in Matlab, and then


amplified and take the round figure with certain bit.
 Achieve multi-stage delay for the input signal by introducing
multiple variables.
 Introduce for loop to reduce the VHDL code editing load.
 It multiplies or divides a constant in the operation in order to
increase or decrease the parameter in order to avoid that some figure
is too large or too small. (in order to reduce the consumption of logical
resource, the constant is generally 2n such as 64, 128, etc. )
FPGA implementation of the digital receiver CEIEC

IFFT
IFFT is realized by SFT, that is, take the conjugation for the input and
output of FFT.
As the input is parallel, it is advised to adopt FFTIP core which is applied
for serial input.
Twiddle factor is calculated and saved in the FPFA register in advance.
The data with certain bit could be obtained by the amplification and
rounding.
Base 2 or base 4 structure could be applied based on the FFT points,
which can achieved in the Matlab simulation.
CEIEC

The block diagram of the digital channelization

You might also like