Dynamic Programming and Some VLSI CAD Applications: Shmuel Wimer
Dynamic Programming and Some VLSI CAD Applications: Shmuel Wimer
Shmuel Wimer
Bar Ilan Univ. Eng. Faculty
Technion, EE Faculty
T
t i, j
there exists a subset A a1 , a2 , , ai , aA
s a j
F otherwise
t 1, j T iff either j 0 or j s a1 . For 1 i n and 0 j B 2 t i, j T
s a1 1, s a2 9, s a3 5, s a4 3 and s a5 8.
j
0 1 2 3 4 5 6 7 8 9 10 11 12 13
i
1 T T F F F F F F F F F F F F
2 T T F F F F F F F T T F F F
3 T T F F F T T F F T T F F F
4 T T F T T T T F T T T F T T
5 T T F T T T T F T T T T T T
s a1 s a2 s a4 1 9 3 13 26 2 s a3 s a5
i=1 2 3 4 5 6 i=1 2 3 4 5 6
15125 10500 5375 3500 5000 0 3 3 3 5 5
J=6 J=6
m[1..6,1..6] s[1..6,1..6]
s t
t3 t5
t3
t1 t4
t1 t1
t2 t2
cost v min cost m uL m cost u ;
mM v
}}
? ?
? ? ? ?
u,q u,q
Problem 1: max
buffer insertions
min q d v, u by buffer insertion at internal nodes.
i i i
Buffer reduces load delay but adds internal delay, power and area.
Problem 2: max
buffer insertions
min q d v, u , s.t. power and area constraints.
i i i
R3
C6
3
C2
R7 7
k - nodes along path from root to node k
C7
with buffer
1
TK TK Dbuffer Rbuffer LK RK Cbuffer RK CK
2
LK Cbuffer CK
solutions are obtained at root, from which an optimal one is chosen. Nodes
of buffer insertion are obtained by top-down backtracking.
LM LN L’K
+ =
TM TN T’K
driver’s receiver’s
resistance load
line-to-line
line resistance coupling
line-to-line
coupling
Using Elmore delay model, simple, inaccurate but with high fidelity
σ1
Si
σi Ri Wi Ci
Si+1
A
L
σn-1
σn
signal’s delay:
Pi si 1 , wi , si i wi i 1 si 1 1 si , 1 i n
1i n
P s , w i 1 Pi si 1 , wi , si
n
Subject to:
i1 w0 i0 si A
n n
In 32nm node and beyond spaces and widths are very few discrete values
Continuous optimization and its well-known results are invalid. The sizing
problem is NP-complete. A pseudo polynomial resource allocation dynamic
programming solution is suitable.
: w0 , s0 ,..., wj , sj is dominant and : w0, s0,..., wj , sj is redundant if:
j
1. A0.. j j
i0 si i0 wi i0 si i0 wi
j j
j
A0..
2. sj sj
3. D D and P P
B1 B2 B8 B7
B2 B8
B9 B1 B7
B9
B12 B10
B5 B10
B3
B3 B5 B4 B12
B6 B11
B11
B6
B4
Vertices - vertical lines. Arcs - rectangular areas where blocks are embedded.
A dual graph is implied.
May 2012 Dynamic Programming 34
From Floorplan to Layout
– Blocks are not perfectly matched, thus white area (waste) results
• Different block sizes yield different layout area, even if block sizes
are area invariant.
v
B B B B
1 2 8 7
h h
B
9 v v v v
B12 B10
h h h h
B B B B12
B B 1 2 7
3 5 B11
B
B 6 B B B B B B B10 B11
4 3 4 5 6 8 9
corresponding to 2 orientations.
+ =
+ =
hparent max hleft , hright
wparent wleft wright
+ =
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
a a a a a a a
Vss
Vss
Vss
Vss
Vss
Vss
b b Vss b b b
b b
a c a c
abutment cost
b d b d
a c a c
d b d b
c a c a
d b d b
c a c a
b d b d
• New litho rules in 32nm and smaller feature size offer many
optimization opportunities.
maximize i 1 pi xi ,
n
all allocations
ci xi K
n
i 1
subject to:
0 xi B, 1 i n
the problem.
max x B p1 x , j 1
f j, y
max x B p j x f j 1, y c j x , 1 j n
maximize i 0 pi xi ,
n
all allocations
Hence f y max p j f y c j , y 1,
j |c j y
, K.
May 2012 Dynamic Programming 49