8085 Microprocessor Architecture

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 8085 Microprocessor
External Pins of the 8085 can be broadly divided in following
categories
• Address and Data Bus
• Control Signals
• Power Supply and Clock Frequency
• Interrupts and Peripheral Initiated Signals
• Reset Signals
• Reset Signals
• Serial I/O Ports

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 Address and Data Bus
The address bus has 8 signal lines, A8-A15, which are
unidirectional.
The other 8 address bits are multiplexed (time shared) with
data bits in AD0-AD7.
 The bits AD0-AD7 are bidirectional and serve as A0-A7
and D0-D7 at the same time.
 During the execution of the instruction, these lines carry
the address bits during the early part, then during the
late parts of the execution, they carry the 8 data bits.
 In order to separate the address from the data, we can use a
latch to save the value before the function of the bits
changes.

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 Control Signals

• ALE – Address Latch Enable: This signal is a pulse

that become 1 when the AD0 – AD7 lines have an
address on them. It becomes 0 after that.

• IO/M – It is a status signal which determines whether

the address is for input-output or memory. When it is
high(1) the address on the address bus is for input-
output devices. When it is low(0) the address on the
address bus is for the memory.

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 Control Signals
• RD – It is a signal to control READ operation. When it
is low the selected memory or input-output device is
read.
• WR – It is a signal to control WRITE operation. When
it goes low the data on the data bus is written into the
selected memory or I/O location.
• READY – It senses whether a peripheral is ready to
transfer data or not. If READY is high(1) the
peripheral is ready. If it is low(0) the microprocessor
waits till it goes high. It is useful for interfacing low
speed devices.
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 Control Signals

• SO, S1 – These are status signals. They distinguish

the various types of operations such as halt, reading,
instruction fetching or writing.

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 Power Supply and Clock Frequency

• Vcc – +5v power supply

• Vss – Ground Reference
• XI, X2 – A crystal is connected at these two pins. The
frequency is internally divided by two, therefore, to
operate a system at 3MHZ the crystal should have
frequency of 6MHZ.
• CLK (OUT) – This signal can be used as the system
clock for other devices.

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 Interrupts and Peripheral Initiated
Signals
The 8085 has five interrupt signals that can be used to interrupt a program
execution.
(i) INTR
(ii) RST 7.5
(iii) RST 6.5
(iv) RST 5.5
(v) TRAP
The microprocessor acknowledges Interrupt Request by INTA’ signal.
• INTR – It is an interrupt request signal.
• INTA’ – It is an interrupt acknowledgment sent by the microprocessor after
INTR is received.
In addition to Interrupts, there are three externally initiated signals namely
RESET, HOLD and READY. To respond to HOLD request, it has one signal
called HLDA.
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 Reset Signals

• RESET IN’ – When the signal on this pin is low(0), the

program-counter is set to zero and the microprocessor unit
is reset.
• RESET OUT – The signal can be used to reset other
supporting devices connected to 8085.

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 DMA Signals

• HOLD – It indicates that another device is requesting the

use of the address and data bus. Having received HOLD
request the microprocessor relinquishes the use of the
buses as soon as the current machine cycle is completed.
Internal processing may continue. After the removal of the
HOLD signal the processor regains the bus.
• HLDA – It is a signal which indicates that the hold request
has been received after the removal of a HOLD request,
the HLDA goes low.

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 DMA Signals
• HOLD: Whenever an externally connected peripheral I/O
Device wants to transmit/receive any data from the
internal-memory of 8085 microprocessor, it requires to use
HOLD pin of 8085.
• External device has to set input High to the HOLD pin,
then 8085 leave the control of buses and transfers the
control to the external device and sets HLDA high.
• By this method external device can fetch data from internal
memory of 8085 using data and address bus. If external
device has to transfer control of buses back to 8085, it set
HOLD again low.
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 Serial I/O Ports

Serial transmission in 8085 is implemented by the two

signals,
• SID and SOD – SID is a data line for serial input where as
SOD is a data line for serial output.

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 The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU – Micro Processing Unit)
communicates with the other units using a 16-bit address
bus, an 8-bit data bus and a control bus.

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 The 8085 Bus Structure

Address Bus
 Consists of 16 address lines: A0 – A15

 Operates in unidirectional mode: The address

bits are always sent from the MPU to peripheral
devices, not reverse.

 16 address lines are capable of addressing a

total of 216 = 65,536 (64k) memory locations.

 Address locations: 0000 (hex) – FFFF (hex)

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 The 8085 Bus Structure
Data Bus
 Consists of 8 data lines: D0 – D7
 Operates in bidirectional mode: The data bits are
sent from the MPU to peripheral devices, as well
as from the peripheral devices to the MPU.

 Data range: 00 (hex) – FF (hex)

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 The 8085: CPU Internal Structure

The internal architecture of the 8085 CPU is

capable of performing the following operations:

 Store 8-bit data (Registers, Accumulator)

 Perform arithmetic and logic operations (ALU)

 Test for conditions (IF / THEN)

 Sequence the execution of instructions

 Store temporary data in RAM during execution

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 The 8085: CPU Internal Structure

Simplified block diagram

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 The 8085: Registers

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 The 8085: CPU Internal Structure
Registers
 Six general purpose 8-bit registers: B, C, D, E, H, L

 They can also be combined as register pairs to

perform 16-bit operations: BC, DE, HL
 Registers are programmable (data load, move, etc.)
Accumulator
 Single 8-bit register that is part of the ALU !
 Used for arithmetic / logic operations – the result is
always stored in the accumulator.
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 The 8085: CPU Internal Structure

Program Counter (PC)

• Contains the memory address (16 bits) of the
instruction that will be executed in the next step.
• When a byte (machine code) is being fetched, the
program counter is incremented by one to point to the
next memory location.

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 Stack Pointer (SP)

 Stack is a buffer which is used to store data from top

to down in memory.
 It points to a memory location in R/W memory, called
the stack.
 The beginning of the stack is defined by loading a
16-bit address in the stack pointer
• Stack pointer is a small register that is used to store
the address of last program accessed by stack.

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 Flag Register

• The Flag register is a Special Purpose Register.

• Depending upon the value of result after any
arithmetic and logical operation the flag bits become
set (1) or reset (0).
• In 8085 microprocessor, flag register consists of 8
bits and only 5 of them are useful.

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 Sign Flag (S)

• After any operation if the MSB (B(7)) of the

accumulator is 1, it indicates the number is negative
and the sign flag becomes set, i.e. 1.
• If the MSB of accumulator is 0, it indicates the
number is positive and the sign flag becomes reset
i.e. 0.

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 Example

• MVI A 30 (load 30H in register A)

MVI B 40 (load 40H in register B)
SUB B (A = A – B)
These set of instructions will set the sign flag to 1 as
30 – 40 is a negative number.
• MVI A 40 (load 40H in register A)
MVI B 30 (load 30H in register B)
SUB B (A = A – B)
These set of instructions will reset the sign flag to 0
as 40 – 30 is a positive number.

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 Zero Flag (Z)

• After any arithmetical or logical operation if the result

is 0 (00)H, the zero flag becomes set i.e. 1, otherwise
it becomes reset i.e. 0.
00H zero flag is 1.

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 Example

• MVI A 10 (load 10H in register A)

SUB A (A = A – A)
These set of instructions will set the zero flag to 1 as
10H – 10H is 00H

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 Auxiliary Cary Flag (AC)
• This flag is used in BCD number system(0-9). If after
any arithmetic or logical operation D(3) generates
any carry and passes on to B(4) this flag becomes
set i.e. 1, otherwise it becomes reset i.e. 0.
• This is the only flag register which is not accessible
by the programmer1-carry out from bit 3 on addition
or borrow into bit 3 on subtraction
0-otherwise

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 Parity Flag (P)

• If after any arithmetic or logical operation the result

has even parity i.e. an even number of 1 bits, the
parity register becomes set i.e. 1, otherwise it
becomes reset i.e. 0
• 1-accumulator has even number of 1 bits
0-accumulator has odd parity

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 Carry Flag (CY)

• Carry is generated when performing n bit operations

and the result is more than n bits, then this flag
becomes set i.e. 1, otherwise it becomes reset i.e. 0.

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 Interrupts

• When microprocessor receives interrupt signals, it

sends an acknowledgement (INTA) to the peripheral
which is requesting for its service.
• Interrupts can be classified into various categories
based on different parameters:
• Hardware and Software Interrupts
• Vectored and Non-Vectored Interrupts
• Mask-able and Non-Mask-able Interrupts

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 Hardware and Software Interrupts

• When microprocessors receive interrupt signals

through pins (hardware) of microprocessor, they are
known as Hardware Interrupts. There are 5 Hardware
Interrupts in 8085 microprocessor. They are – INTR,
RST 7.5, RST 6.5, RST 5.5, TRAP
• Software Interrupts are those which are inserted in
between the program which means these are
mnemonics of microprocessor. There are 8 software
interrupts in 8085 microprocessor. They are – RST 0,
RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.

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 Vectored and Non-Vectored Interrupts

• Vectored Interrupts are those which have fixed vector

address.
• Non-Vectored Interrupts are those in which vector
address is not predefined.

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 Mask-able Interrupts

• Mask-able Interrupts are those which can be disabled

or ignored by the microprocessor.
• These interrupts are either edge-triggered or level-
triggered, so they can be disabled.
• INTR, RST 7.5, RST 6.5, RST 5.5 are mask-able
interrupts in 8085 microprocessor.

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 Non-Mask-able Interrupts

• Non-Mask-able Interrupts are those which cannot be

disabled or ignored by microprocessor.
• TRAP is a non-mask-able interrupt. It consists of both
level as well as edge triggering and is used in critical
power failure conditions.

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 Instruction register and decoder

• It is an 8-bit register.
• When an instruction is fetched from memory then it is
stored in the Instruction register.
• Instruction decoder decodes the information present
in the Instruction register.

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 Example: Memory Read Operation

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 Example: Instruction Fetch Operation

 All instructions (program steps) are stored in memory.

 To run a program, the individual instructions must

be read from the memory in sequence, and executed.

 Program counter puts the 16-bit memory address of the

instruction on the address bus
 Control unit sends the Memory Read Enable signal to
access the memory
 The 8-bit instruction stored in memory is placed on the data
bus and transferred to the instruction decoder
 Instruction is decoded and executed

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 Example: Instruction Fetch Operation

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 Example: Instruction Fetch Operation

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 8085 Functional Block Diagram

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 Addressing Modes

• Various ways of specifying the operands or various

formats for specifying the operands is called
addressing mode.
• 8-bit or 16-bit data may be directly given in the
instruction itself.
• The address of the memory location, I/O port or I/O
device, where data resides, may be given in the
instruction itself.
• In some instructions only one register is specified.
The content of the specified register is one of the
operands. It is understood that the other operand is in
the accumulator.
 Addressing Modes

• Some instructions specify one or two registers. The

contents of the registers are the required data.
• In some instructions data is implied. The most
instructions of this type operate on the content of the
accumulator.
• Addressing modes in 8085 is classified into 5 groups
 Addressing Modes in 8085

• Immediate addressing mode

• Register addressing mode
• Direct addressing mode
• Indirect addressing mode
• Implied addressing mode

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 Immediate addressing mode

• In this mode, the 8/16-bit data is specified in the

instruction itself as one of its operand.
• Example: MVI K, 20F: means 20F is copied into
register K.

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 Register addressing mode

• In this mode, the data is copied from one register to

another.
• Example: MOV K, B: means data in register B is
copied to register K.

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 Direct addressing mode

• In this mode, the data is directly copied from the

given address to the register.
• Example: LDB 5000: means the data at address
5000 is copied to register B.

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 Indirect addressing mode

• In this mode, the address of the operand is specified

by a register pair.
Example: LXI H, 2500 : means load H-L pair with 2500
H.

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 Implied addressing mode

The microprocessor compares a data byte (or

register/memory contents) with the contents of the
accumulator by subtracting the data byte from (A), and
indicates whether the data byte is less than, greater
than or equals to the content of accumulator by
modifying the flags.
However, the contents are not modified

Example: CMP, CPI

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