Design Process

Salahuddin Ahmed
Design Flow
Design Conception

Design Entry
Schematic HDL
Capture Entry

Synthesis

Functional Simulation

No Design
Correct ?
Yes

Physical Design

Timing Simulation

No Timing
Met ?
Yes

Chip Configuration
Design Specification
 Algorithm to be implemented with
mathematical representation
 Number of IOs and number of bits in
each IO
 Number of bits in internal arithmetic
operation
 Number of clock signals in the design
 Maximum clock frequency
 Area of the chip
 Power dissipation of the chip
Design Entry
 Architectural decision  Schematic Entry:
is to be taken first  Place components
 Number of sub-  Interconnect
blocks, their components
functionality and  Name IOs
interconnects
 HDL Entry:
 Type of processing,  Two dominant HDL:
serial or parallel
 VHDL
 If pipelined, number  Verilog HDL
of stages and
operation in each  Describes digital
stage hardware as:
 Structural Model
 Design entry are of
 Behavioral Model
two types:
 In Verilog, each
 Schematic entry variable can have ‘0’,
‘1’, ‘x’ or ‘z’ values
 HDL entry
Synthesis
Functional Simulation
 Verifies the correctness of the design
 There may be two types of errors:
 Logic expression derived for implementing
a function may be erroneous.
 Due to human error there may be
unconnected nets, undue duplication of
names or syntax error
 To find errors and their location,
stimulus is given at the input and,
output response is observed.
 Stimulus can be given as:
 Test vectors
 Commands (by using command file)
Physical Design
 a.k.a Place and Route (P&R) phase
 Determines physical location of devices
and their interconnects inside the IC.
 One of the main aims is to minimize
the circuit area to reduce fabrication
cost.
 Smaller the chip area, fewer the defects
and larger the yield.
 Other goals are:
 Delay minimization
 Power minimization
 Wire length minimization
 Via minimization
Physical Design (cont.)
 Various parts of physical design phase are
 Partitioning
 Divide the top module into reasonable sub-
modules
 Also minimize the interconnect among sub-
modules
 Floorplanning
 Shape each sub-module
 IO Pin placement at the boundary of sub-modules
 Approximate location of each sub-module in
rectangular IC
 Memory and Macro (soft and hard) placement
 Target is to reduce chip area, improve
performance and simpler routing phase.
Physical Design (cont.)
 Various parts of physical design phase are
 Power Planning
 Power ring/stripe generation to create PG mesh
for the core area
 Power pin connection for memory/hard macro
 Power rail generation for standard cell
 Target is to even distribution of power across the
chip, minimize IR drop and Electromigration
 Placement
 Placement of standard cells
 Design optimization to reduce timing violation
(setup & hold)
 CTS and placement to reduce clock skew
Physical Design (cont.)
 Various parts of physical design phase are
 Routing
 Clock tree routing to interconnect clock buffers
and memory elements (flops, latches, ram/rom,
PLL etc.)
 Target is to minimize clock skew.
 Signal nets routing to interconnect the
components
 Minimize wire-length, via count and chip area.
 Routing is performed in two steps:
 Global routing
 Detailed routing
 Minor optimization is also done to fix timing
violation (setup & hold)
Timing Simulation
 After P&R phase net/gate delay come into
account
 Time for a signal to travel from one gate to the
next is net delay
 Propagation time (from input to output) of the
gate is gate delay
 Timing simulation is done at clock speed to see
if the design meets the timing constraints.
 Procedure is similar to functional simulation
 Functionally correct design may fail in timing
verification
 Timing analysis is done to see the timing
performance of a circuit such as setup and
hold time of flip-flops are met
 Gives an idea of max clock frequency for the
design.
Fabrication Into the Chip
 Two different VLSI design styles:
 Full Custom
 Chips are ASICs, designed specifically for given
application or application domain.
 Complete design is hand-crafted in transistor
level to optimize the circuit for performance
and area
 Semi Custom, also two types:
 Cell based
 Use libraries of predefined cells that are placed
and routed
 Array based
 Use prefabricated matrix of non-connected
components
 FPGA uses programmable logic modules and
programmable interconnections.
Mask Generation
 In IC design the final step is the
mask generation phase.
 Masks are geometric patterns, used
for etching in lithography.
 Mask is generated using technology
files of targeted foundry.
 Output mask data of the design
process is sent to foundry to
manufacture the chip.
Tapeout to Foundry
 After design is complete chip is taped
out.
 Magnetic tape were used to transfer masks
to foundry, hence the name tapeout.
 Two common formats are used for mask
descriptions:
 Caltech Interchange Format (CIF)
 Calma GDS II Stream Format (GDS II)
 Masks are made by etching a pattern of
chrome on glass with an electron beam.
 Cost is astronomical, in the range of Million $
 Well-known fab companies are TSMC,
UMC, Global Foundries etc.
Fab, Packaging and Testing
 Multiple chips are manufactured at
the same time on a single wafer.
 Processed wafers are sawed into dice
(chips) and packaged.
 Wire-bonded package uses thin gold
wires to connect the pads on the die
 Flip-chip technology places small
solder balls directly onto the die,
eliminating the bond wire inductance
 Chips are tested before being sold.
 BIST is used to reduce tester time, thus
cost