Memory

It is a storage device used to hold the

input and Data.
 Nonvolatile Memories
• DRAM and SRAM are volatile memories
– Lose information if powered off.
• Nonvolatile memories retain value even if powered off.
– Generic name is read-only memory (ROM).
• Types of ROMs
– Programmable ROM (PROM)
– Eraseable programmable ROM (EPROM)
– Electrically eraseable PROM (EEPROM)
– Flash memory
 Random-Access Memory (RAM)
• Key features
– RAM is packaged as a chip.
– Basic storage unit is a cell (one bit per cell).
– Multiple RAM chips form a memory.
• Static RAM (SRAM)
– Each cell stores bit with a six-transistor circuit.
– Retains value indefinitely, as long as it is kept powered.
– Relatively insensitive to disturbances such as electrical noise.
– Faster and more expensive than DRAM.
• Dynamic RAM (DRAM)
– Each cell stores bit with a capacitor and transistor.
– Value must be refreshed every 10-100 ms.
– Sensitive to disturbances.
– Slower and cheaper than SRAM.
 Enhanced DRAMs
• All enhanced DRAMs are built around the conventional DRAM
core.

– Synchronous DRAM (SDRAM)

• Driven with rising clock edge instead of asynchronous control signals.
– Double data-rate synchronous DRAM (DDR SDRAM)
• Enhancement of SDRAM that uses both clock edges as control signals.
– Video RAM (VRAM)
• Dual ported (allows concurrent reads and writes)
 Typical Bus Structure Connecting
CPU and Memory
• A bus is a collection of parallel wires that carry address, data,
and control signals.
• Buses are typically shared by multiple devices.

CPU chip

register file

ALU

system bus memory bus

I/O main
bus interface
bridge memory
 Memory Read Transaction (1)

• CPU places address B on the memory bus.

register file Load operation: mov B, M

ALU
B

main memory
I/O bridge 0

bus interface x M
 Memory Read Transaction (2)
• Main memory reads M from the memory bus, retrieves word
x, and places it on the bus.
register file
Load operation: mov B, M

ALU
B

main memory
I/O bridge x 0

bus interface x M
 Memory Read Transaction (3)
• CPU read word x from the bus and copies it into register
%eax.
register file
Load operation: mov B, M

ALU
B x

main memory
I/O bridge 0

bus interface x M
 Memory Write Transaction (1)
• CPU places address M on bus. Main memory reads it and
waits for the corresponding data word to arrive.
register file Store operation: mov M, B

ALU
B y

main memory
I/O bridge 0
M
bus interface M
 Memory Write Transaction (2)

• CPU places data word y on the bus.

register file Store operation: mov M, B

ALU
B y

main memory
I/O bridge 0
y
bus interface M
 Memory Write Transaction (3)
• Main memory read data word y from the bus and stores it at
address A.
register file Store operation: mov M, B

ALU
B y

main memory
I/O bridge 0

bus interface y M
CPU chip
Reading a Disk Sector (1)
CPU initiates a disk read by writing a
register file
command, logical block number, and
• ALU
destination memory address to a port
(address) associated with disk controller.

main
bus interface
memory

I/O bus

USB graphics disk

controller adapter controller

mouse keyboard monitor

disk
CPU chip
Reading a Disk Sector (2)
Disk controller reads the sector and performs
register file
a direct memory access (DMA) transfer into
main memory.
ALU

main
bus interface
memory

I/O bus

USB graphics disk

controller adapter controller

mouse keyboard monitor

disk
CPU chip
Reading a Disk Sector (3)
When the DMA transfer completes, the disk
register file
controller notifies the CPU with an interrupt
(i.e., asserts a special “interrupt” pin on the
ALU
CPU)

main
bus interface
memory

I/O bus

USB graphics disk

controller adapter controller

mouse keyboard monitor

disk
 An Example Memory Hierarchy
Smaller, L0:
faster, registers CPU registers hold words retrieved from L1
and cache.
costlier L1: on-chip L1
(per byte) cache (SRAM) L1 cache holds cache lines retrieved from
storage the L2 cache memory.
devices L2: off-chip L2
cache (SRAM) L2 cache holds cache lines retrieved
from main memory.

L3: main memory

Larger, (DRAM)
Main memory holds disk
slower, blocks retrieved from local
and disks.
cheaper local secondary storage
L4:
(per byte) (local disks)
storage Local disks hold files retrieved
from disks on remote
devices network servers.

L5: remote secondary storage

(distributed file systems, Web servers)
 Disk Capacity

• Capacity: maximum number of bits that can be stored.

– Vendors express capacity in units of gigabytes (GB), where 1 GB = 10^9.

• Capacity is determined by these technology factors:

– Recording density (bits/in): number of bits that can be squeezed into a 1 inch
segment of a track.
– Track density (tracks/in): number of tracks that can be squeezed into a 1 inch
radial segment.
– Areal density (bits/in2): product of recording and track density.

• Modern disks partition tracks into disjoint subsets called recording zones

– Each track in a zone has the same number of sectors, determined by the
circumference of innermost track.
– Each zone has a different number of sectors/track
 Computing Disk Capacity
• Capacity = (# bytes/sector) x (avg. # sectors/track) x
• (# tracks/surface) x (# surfaces/platter) x
• (# platters/disk)
• Example:
– 512 bytes/sector
– 300 sectors/track (on average)
– 20,000 tracks/surface
– 2 surfaces/platter
– 5 platters/disk

• Capacity = 512 x 300 x 20000 x 2 x 5

• = 30,720,000,000
• = 30.72 GB
 Caches
• Cache: A smaller, faster storage device that
acts as a staging area for a subset of the data
in a larger, slower device.
 Chip characteristics
• Density: Size of the chip in megabits. For example, 256 Mbit,
or 32 MB chip. Nearly all motherboards only recognize 1 GB
modules if they are low density 64M×8 modules. If high
density 128M×4 1 GB modules are used, they most likely will
not work

• Organization
 Module characteristics
• Capacity (Number of DRAM Devices)
• ECC vs non-ECC Modules that have error correcting code are labeled as ECC. Modules without error
correcting code are labeled non-ECC.

• Number of DRAM Ranks (also known as rows or sides) Any given module can have 1, 2, or 4 ranks,
but only 1 rank of a module can be active at any moment in time. When a module has two or more ranks, the
memory controller must periodically switch between them by performing close and open operations.

• Timings latency, clock cycle time, row cycle time, refresh row cycle time, row active time
• Buffering

• Packaging

• Power consumption
 Caching in a Memory Hierarchy
Level k: 48 9 14
10 3

Data is copied between

10
4 levels in block-sized transfer units

0 1 2 3

Level k+1: 4 5 6 7

8 9 10 11

12 13 14 15
 General Caching Concepts
• Program needs object d, which is stored in
Request
14
12 some block b.
12
14
0 1 2 3
• Cache hit
Level 4*
12 9 14 3 – Program finds b in the cache at level k. E.g.,
k: block 14.
• Cache miss
12
4* Request
12 – b is not at level k, so level k cache must fetch
it from level k+1. E.g., block 12.
– If level k cache is full, then some current block
0 1 2 3
must be replaced (evicted). Which one is the
“victim”?
Level 4
4* 5 6 7
k+1: 8 9 10 11
12 13 14 15
 General Caching Concepts
• Types of cache misses:
– Cold (compulsory) miss
• Cold misses occur because the cache is empty.
– Conflict miss
• Conflict misses occur when the level k cache is large enough,
but multiple data objects all map to the same level k block.
• E.g. Referencing blocks 0, 8, 0, 8, 0, 8, ... would miss every
time.
– Capacity miss
• Occurs when the set of active cache blocks (working set) is
larger than the cache.