DFT definition

• DFT (Design For Test) is design technique for manufacturing testing.

In order to test any device, it is necessary to have the ability to control the
product and to observe the output response. The device must enter into a known
state, before input data can be supplied. The output is observed and compared
to ensure the device performs as it was designed and manufactured
 DFT Methods
• Build-in self-test (BIST) : BIST involves adding test circuitry for generating test
patterns on-chip and verifying response on-chip
• Build-out self-test (BOST)
 What is Boundary Scan ?

Boundary scan is a method for testing interconnects on PCBs and

internal IC sub-blocks. It is defined in the IEEE 1149.1 standard
Boundary Scan
Boundary Scan
 Benefits of Boundary Scan

Adding boundary scan logic to your board lets you detect the vast majority of
board manufacturing process faults :
- wrong components
- missing components
- misoriented components
- components with stuck pins
- shorts, opens
- blown wire bonds
 Advantages of BS

• It’s a standard! (IEEE 1149.1)

– allows mixing components from different vendors
– provides excellent interface to internal circuitry
• Allows testing of board & system interconnect
– back-plane interconnect test w/o using PCB functionality
– very high fault coverage for interconnect
• Useful in diagnosis & FMA
– provides component-level fault isolation
– allows real-time sampling of devices on board
– useful at wafer test (fewer probes needed)
• BS path reconfigured to bypass ICs for faster access
 Disadvantages of BS
• Overhead
• The extra circuitry will cause additional gate delays, which could affect
device specifications
• Boundary-scan and internal scan can be implemented so that both
could be used at the same time allowing for the reduction of required
signals to only the four TAP signals. The boundary-scan register could
therefore easily control and observe the inputs and outputs to the
core logic
• BIST could be used with boundary-scan and internal scan as a quick
method for pass or fail testing while the scan path is used for debug
and failure diagnosis
• Boundary-scan allows for compatibility with other vendors, since it is
an IEEE standard
Simple boundary scan architecture
 Test Access Port (TAP)
• TAP consisting of the following signals:
- TDI : Test Data In
- TDO : Test Data Out
- TMS: Test Model Select
- TCK: Test Clock
- TRST : Test Reset(optional)
• TAP controller is a finite state machine with 16 states
 Test Data Registers
• Boundary Scan Register (Mandatory)
• Bypass Register (Mandatory)
• Instruction Register (Mandatory)
• Device-id Register (Optional)
• Design Specific Registers (Optional)
 Data Registers

• Boundary Scan Register

- the connection of the individual boundary scan
cells
• Bypass register
- a one-bit register used to pass test signal from a
chip when it is not involved in current test operation.
 Instruction Register

The instruction register controls the boundary scan circuitry by connecting

a specific test data register between the TDI and TDO pins and controlling
the operation affecting the data in that register, using a predefined set of
instructions

Boundary scan devices can perform many test functions. Three of these, EXTEST,
SAMPLE/PRELOAD, and BYPASS, are mandatory for every boundary-scan device.
For other test functions, INTEST, RUNBIST, IDCODE, CLAMP, HIGHZ, and USERCODE,
are described by the IEEE 1149.1 standard, but are optional.
 Optional Test Data Registers
• Device identification (optional)
The device identification register contains a device identification code
or programming code used to check that the board has the proper
chips.
• Data-specific (optional)
These registers allow access to the chip’s test support features, such
as BIST and internal scan paths
 Boundary Scan Cell architecture
• Boundary Scan Cells contain memory elements for capturing data
from the circuit, loading data into the circuit, or serially shifting data to
the next scan cell in the path.
EXTEST
BYPASS
INTEST
Following boundary scan instructions are defined in the IEEE standard:
• BYPASS (mandatory): TDI is connected to TDO via a single shift register.
• SAMPLE (mandatory): Takes a snapshot of the normal operation of the IC.
• PRELOAD (mandatory): Loads data to the boundary scan register.
• EXTEST (mandatory): to test external interconnect between ICs.

• INTEST (optional): to test internal logic within the IC.

• RUNBIST (optional): Executes a self-contained self-test of the IC.
• CLAMP (optional): Apply preloaded data of the boundary scan register to the
ports and selects the bypass register as the serial path between TDI and TDO.
• IDCODE (optional): Reads the device identification register.
• USERCODE (optional): Reads and writes a user programmable identification
register.
• HIGHZ (optional): Places the IC in an inactive drive state (e.g. all ports are set to
high impedance state).
 What is BS needed ?
• Typically the test programme generator requires :
 The net-list of the Unit Under Test (UUT)
 The Boundary Scan Description Language (BSDL) files of the
boundary scan components contained within the circuit.
With this information it is possible for the test programme generator to
create the test patterns used for the test. These allow the system to
detect and isolate any faults for all boundary-scan testable nets within
the circuit. It is also possible for the test programme generator to
create test vectors that enable the system to detect faults on the nodes
or pins components non-boundary scan components that are
surrounded by boundary scan devices
Boundary Scan Flow
Boundary Scan Description Language (BSDL)
The Boundary Scan Description Language enables users to provide a description of the way in which boundary scan applies to
different devices.
• Entity Declaration: The Entity Declaration is a VHDL construction that is used to identify the name of the device that is
described by the BSDL file.
• Generic Parameter: The Generic Parameter is the section of the BSDL file that specifies which package is described.
• Logical Port Description: This description lists all the connections on the device. It defines its basic attributes, i.e.
whether the connection is an input (in bit;), output (out bit;), bi-directional (in-out bit;) or if it is unavailable for boundary
scan (linkage bit;).
• Package Pin Mapping: The Package Pin Mapping is used for determining the internal connections within an integrated
circuit. It details how the pads on the device die are wired to the external pins.
• Use statements: This statement is used to call the VHDL packages that contain the data that are referenced in the BSDL
File.
• Scan Port Identification: The Scan Port Identification identifies the particular pins that are used for the boundary scan /
JTAG implementation. These include: TDI, TDO, TMS, TCK and TRST (if used).
• TAP description: This entity provides additional information on the boundary scan or JTAG logic for the device. The data
included comprises: the Instruction Register length, Instruction Opcodes, device IDCODE, etc.
• Boundary Register description: This description provides the structure of the Boundary Scan cells on the device. Each pin
on a device may have up to three Boundary Scan cells, each cell consisting of a register and a latch.