Research Engineering Services Technologies

Case study – Capacitor Bank Switching

Transients
Dharshana Muthumuni
Manitoba HVDC Research Center
 The Design Problem

 Install capacitor banks at a 500/230 kV high voltage

transmission system to support the voltage by providing
capacitive reactive power.
 The capacitors are to be installed in 4 banks.
 Each back has a rating of 75 MVAR
 Each bank can be independently switched on and off from
the system depending on the system requirements.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 2

 The Design Problem

 The main breaker should be able to interrupt the current in

the event of faults.
 The breakers in the individual banks should be able to
withstand normal switching transients.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 3

 Page 4
Case Study - Capacitor Bank Switching Transients
Capacitors
Breakers
The Design Problem

Main Breaker

Inrush Capacitor
0.05994 [MW] Reactor 25 MVars per phase/step
-4.254e-005 [MVAR]

R4
0.000277 3.76

R4
Inrush Capacitor
0.1155 [MW] Reactor 25 MVars per phase/step
-83.88 [MVAR]

R3
0.000277 3.76
Reactors
Outrus h
0.3425 [MW]
-168.3 [MVAR]
TO 230 kV

Open@t0
GT230

Breaker
Tim ed
BUS

Logic
GTVcap 0.00317 Inrush Capacitor
RL 0.05994 [MW] Reactor 25 MVars per phase/step
-4.254e-005 [MVAR]

RL

R2
R2 0.000277 3.76

RL

R2
Inrush Capacitor
0.05876 [MW] Reactor 25 MVars per phase/step
-85.02 [MVAR]

R1
R1 0.000277 3.76

July 3, 2019
R1
 Major issues

The most common transient problems associated with

capacitor banks are
• Over voltage during energization.
• Voltage magnification at low voltage capacitors.
• Transformer phase-phase over-voltages at line
ends during capacitor bank energization.
• Capacitor breaker re-strike.
• Inrush current through breakers when switching
parallel banks.
• Out-rush currents through breakers to nearby
faults.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 5

 Page 6
Determine the value of capacitors.

MVAR,s per bank = 300/4 = 75

MVAR’s per phase = 25

F

Case Study - Capacitor Bank Switching Transients

Q  V  C w

V w

C  3.761
Q
2
2

C 
The Capacitors

Capacitors
Breakers
Main Breaker
Inrush Capacitor
0.05994 [MW] Reactor 25 MVars per phase/step
-4.254e-005 [MVAR]

R4
0.000277 3.76

R4
Inrush Capacitor
0.1155 [MW] Reactor 25 MVars per phase/step
-83.88 [MVAR]

R3
0.000277 3.76

Reactors
Outrush
0.3425 [MW]
-168.3 [MVAR]
TO 230 kV

Open@t0
GT230

Breaker
Timed
BUS

Logic
GTVcap 0.00317 Inrush Capacitor
RL 0.05994 [MW] Reactor 25 MVars per phase/step
-4.254e-005 [MVAR]

RL

R2
R2 0.000277 3.76

RL

R2
Inrush Capacitor
0.05876 [MW] Reactor 25 MVars per phase/step
-85.02 [MVAR]

July 3, 2019
R1
R1 0.000277 3.76

R1
 The Capacitors

TO 230 kV
BUS

GT230 Connection
• Delta or Star
Main Breaker • Grounding considerations
-168.3 [MVAR]
0.3425 [MW]
RL

RL
RL
GTVcap

• Placement
0.00317

Outrush
Reactors

Solidly grounded star

-4.254e-005 [MVAR]

-4.254e-005 [MVAR]

connection is selected for this

-85.02 [MVAR]

-83.88 [MVAR]
0.05876 [MW]

0.05994 [MW]

0.05994 [MW]
0.1155 [MW]
R1

R2

Breakers
Open@t0
Logic
installation.
R1 R2 Breaker R3 R4
R1 R2 Timed R4

May have to be re-evaluated

0.000277

0.000277

0.000277

0.000277
Reactor

Reactor

Reactor

Reactor
Inrush

Inrush

Inrush

Inrush

later in the design process

25 MVars per phase/step

25 MVars per phase/step

25 MVars per phase/step

25 MVars per phase/step

Capacitor

Capacitor

Capacitor

Capacitor
3.76

3.76

3.76

3.76

Capacitors when harmonic problems are

assessed.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 7

 Page 8
The magnitude and frequency
...
...
...
Inrush current

0.2045

of the inrush current are not

0.2040
0.2035

Case Study - Capacitor Bank Switching Transients

R3Ic

0.2030
0.2025
Inrush Current

0.2020
0.2015
R3Ib

acceptable.
0.2010
0.2005
0.2000
R3Ia

0.1995
Back to Back Switching

30

20

10

-10

-20

-30

y
Inrush Capacitor
0.05994 [MW] Reactor 25 MVars per phase/step
-4.254e-005 [MVAR]

R4
0.000277 3.76

R4
Inrush Capacitor
0.1155 [MW] Reactor 25 MVars per phase/step
-83.88 [MVAR]

R3
0.000277 3.76

Reactors
Outrush
0.3425 [MW]
-168.3 [MVAR]
TO 230 kV

Open@t0
GT230

Breaker
Timed
BUS

Logic
GTVcap 0.00317 Inrush Capacitor
RL 0.05994 [MW] Reactor 25 MVars per phase/step
-4.254e-005 [MVAR]

RL

R2
R2 0.000277 3.76

RL

R2
Inrush Capacitor
0.05876 [MW] Reactor 25 MVars per phase/step
-85.02 [MVAR]

R1
R1 0.000277 3.76

July 3, 2019
R1
 Back to Back Switching

Inrush Current

R3Ia R3Ib R3Ic

30 TO 230 kV

The inrush current is limited by

BUS

20
GT230

Inrush current
10
the stray bus inductances and
-168.3 [MVAR]
0.3425 [MW]
RL

the bus resistances.

0 RL
y

RL
GTVcap

-10
0.00317

-20 Outrush
Reactors

-30

0.1995 0.2000 0.2005 0.2010 0.2015 0.2020 0.2025 0.2030 0.2035 0.2040 0.2045 ...
Model the stray L and R based
...
... on station layout
-4.254e-005 [MVAR]

-4.254e-005 [MVAR]

•Station drawings
-85.02 [MVAR]

-83.88 [MVAR]
0.05876 [MW]

0.05994 [MW]

0.05994 [MW]
0.1155 [MW]
R1

R2

R1 R2
Open@t0
Logic
Breaker
Timed
R3 R4
•Typical values from IEEE
R1 R2 R4

guides (IEEE C37.06.2000 -

0.000277

0.000277

0.000277

0.000277
Reactor

Reactor

Reactor

Reactor
Inrush

Inrush

Inrush

Inrush

page 7)
25 MVars per phase/step

25 MVars per phase/step

25 MVars per phase/step

25 MVars per phase/step

Capacitor

Capacitor

Capacitor

Capacitor
3.76

3.76

3.76

3.76

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 9

 Inrush Reactors

Inrush Current

R3Ia R3Ib R3Ic

30

20
Inrush current The peak and the frequency of
10
the inrush current must be
limited to values specified by
0
y

-10

-20 breaker standards. (IEEE

-30

0.1995 0.2000 0.2005 0.2010 0.2015 0.2020 0.2025 0.2030 0.2035 0.2040 0.2045 ...
C37.06.2000 - page 7)
...
...

Additional reactors may be required to limit the

inrush current

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 10

 Inrush Reactor Design

Inrush reactor for back to back switching: Design

KV  230 System rated line to line voltage in kV parameters are
the peak current
75
MVA 
3
MVA  25 per phase MVA per bank and frequency.
MVA
Irat  Irat  0.109 Rated current of a bank in kA
KV

IratAmps  Irat  1000 IratAmps  108.696 Rated current of a bank in A

Tolarance factors:

K_v  1.10 10% overvoltage

Tolerance factors
K_c  1.1 10 % positive tolarance for capacitances
K_h  1.1 Factor for harmonic content

K  K_v  K_c K_h K  1.331

I  IratAmps  K I  144.674

V  KV K_v V  253 Rated maximum voltage

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 11

 Inrush Reactor Design

(IEEE C37.06.2000 - page 7)

V I1 I2
i_max_pk  1747 Peak current
Leq  10  I1  I2
6

fs  V I1  I2
f  9.5
6 Frequency
Leq  10  I1 I2

Check all operation possibilities.

0.6 mH was selected as the reactor size.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 12

 Inrush Reactors

Inrush Current Inrush Current

10.0
R3Ia
Inrush current
R3Ib R3Ic
30
R3Ia R3Ib R3Ic

7.5
20
5.0

2.5 10

0.0
0
y

y
-2.5

-5.0 -10

-7.5
-20
-10.0

-12.5 -30

0.1995 0.2000 0.2005 0.2010 0.2015 0.2020 0.2025 0.2030 0.2035 0.2040 0.2045 ... 0.1995 0.2000 0.2005 0.2010 0.2015 0.2020 0.2025 0.2030 0.2035 0.2040 0.2045 ...
... ...
... ...

With inrush reactor Without inrush reactor

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 13

 Inrush Reactors

Notes:

•The transient current component supplied by the source side is

small and of low frequency and can be neglected. (IEEE
C37.012.1979 - page 17)

•Inductance of the capacitors itself is about 10 uH. (IEEE

C37.012.1979 - page 19)

•Typical bus inductance between banks falls between 85 - 170 uH

at the 230 kV range. This is small compared to the total required
Inrush Inductance.

•See ANSI C37.06.1979 for breaker selection and ratings.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 14

 Out-rush Reactors

TO 230 kV
BUS

GT230
• Limit transient when switching the first
bank.
-168.3 [MVAR]
0.3425 [MW]
RL

RL
RL
GTVcap

• Limit fault current contribution for a

0.00317

Outrush
Reactors
fault at the bus.
-4.254e-005 [MVAR]

-4.254e-005 [MVAR]
-85.02 [MVAR]

-83.88 [MVAR]
0.05876 [MW]

0.05994 [MW]

0.05994 [MW]

230 kV
0.1155 [MW]
R1

R2

Capacitors

Open@t0
Logic
R1 R2 Breaker R3 R4
R1 R2 Timed R4
BUS230-ph
Ph
0.000277

0.000277

0.000277

0.000277
Reactor

Reactor

Reactor

Reactor
Inrush

Inrush

Inrush

Inrush

RRL
F

60.0
25 MVars per phase/step

25 MVars per phase/step

25 MVars per phase/step

25 MVars per phase/step

230 kV Equivalance at the capacitor bus

Z+ = 4.284 Ohms at 88 degrees
V
Capacitor

Capacitor

Capacitor

Capacitor
3.76

3.76

3.76

3.76

Z0 = 4.2 Ohms at 87 degrees

RL

BUS230-V

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 15

 Out-rush Reactors

230 kV
Capacitors
Isolated switching
• Switching of the first bank
BUS230-ph
• Transient current limited by the
Ph

RRL

system impedance, inrush and out-

F

60.0
230 kV Equivalance at the capacitor bus
Z+ = 4.284 Ohms at 88 degrees
V

Z0 = 4.2 Ohms at 87 degrees

rush reactors.
RL

BUS230-V

• Verify if additional out-rush reactors

are required.

In this case, the system impedance was

adequate to limit the transients. Thus, the out-
rush reactor was selected based on the fault
limiting considerations.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 16

 Out-rush Reactors

230 kV
Capacitors
Fault limiting
• Faults at the 230 kV bus will be fed by
BUS230-ph
the capacitors.
Ph

• Limited only by the inrush and out-

RRL
F

60.0
230 kV Equivalance at the capacitor bus
Z+ = 4.284 Ohms at 88 degrees
V

Z0 = 4.2 Ohms at 87 degrees

rush reactors.
RL

BUS230-V

• Worst case is when all banks are in

use.

See Mathcad worksheets for details.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 17

 Out-rush Reactors

Isc
f  fs  f  774.853
I

imax_pk f   2 
didt_max  Max. allowable di/dt for breaker
6 didt_max  21.054 In A/us
10

Allowable maximum rate of change for a breaker with a 40kA interrupting capacity

3
377 40 10  1.4
didt_allow  didt_allow  21.112 In A/us
6
10

Thus , to meet the IEEE guidelines for i solated capacitor switching,

The Thevanins impedance at the 230 kV bus must be
over 3.5 Ohms. If this value is less than 3.5 Ohms, then additional
Outrush reactors must be placed.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 18

 Verify the design with simulation

Voltage at the cap bus

300

200 Initial verification of the capacitor

100

0
bank compliance to the standards.
kV

-100
• Use a reduced network
-200

-300 equivalence at the 230 kV bus

RLIa RLIb RLIc
2.00

1.50

1.00

0.50

0.00 230 kV
kA

-0.50
Capacitors
-1.00

-1.50

-2.00

-2.50 BUS230-ph

Ph
R3Ia R3Ib R3Ic
10.0

RRL
7.5

F
5.0
60.0
2.5
230 kV Equivalance at the capacitor bus
Z+ = 4.284 Ohms at 88 degrees

V
0.0
Z0 = 4.2 Ohms at 87 degrees
kA

-2.5

RL
-5.0 BUS230-V
-7.5

-10.0

-12.5

0.1850 0.1900 0.1950 0.2000 0.2050 0.2100 0.2150 0.2200 0.2250 0.2300 ...
...
...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 19

 Verify the design with simulation

Use the multiple run component

to identify the ‘worst’ case.

• Point on wave switching.

• Number of banks.
• record and analyze data.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 20

Network limits for the switching study

The purpose of the switching study

• Identify TOVs in the network

• Selection of the MOVs
• Breaker TRV study
• Resonance problems
• Dynamic over-voltage problems.

The network beyond the 230 kV capacitor

bus should be modeled in detail.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 21

Network limits for the switching study

Deciding on the network to be modeled in detail:

• Frequency response at the capacitor bus.
• All lines connected to the bus that are over 132 kV.
1800 [Hz]

Harmonic Impedance Profile

0.0 -

0.5 [MVAR]
Z(f)

1400
1200
COUPLED BRK #1 #2
Ipri Isec 1000

Z(Ohms)
FILTER

Ea
0.01

PI 800
.02 [MW]

SECTION 600
400
Filter 200
Iflt
0
0 500 1000 1500 2000
Frequency (Hz)

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 22

Network limits for the switching study

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 23

Network limits for the switching study

MIDWAY 500KV STATION

There was a Cap installed here
C=112.4uF, removed as CAP 7 installed.

-1347 [MW]
110.2 [MVAR]
Midway - Vincent 1 mov mov
COUPLED
I67

The network is arranged in sub pages.

R67 V67 PI
C CAP 7 C SECTION

R67 Midw ay : Controls

R67 R65 R66 R67
C O C O C O

V
Metering MW
V67 P67 P67
Page VT
I Inst Xfmrs
0 0 0
1 and 2
I67 Q67 Q67

-1346 [MW]
108.9 [MVAR]
Midway - Vincent 2 mov mov
COUPLED
I66

R66 V66 PI
C CAP 6 C SECTION

R66
R66

V
V66 Metering P66 P66
Page
I
Inst Xfmrs
I66 Q67 Q66

-1107 [MW]
-208.9 [MVAR]
mov mov
Fault_Loc_EA11

Midway - Vincent 3
MW
I65
VT
V65
R65 3
C CAP 5 C

R65
R65

V65
V
Metering
P65 P65
0.01
A B B
Page

I65
I Inst Xfmrs
Q65 Q65 MW_VT3_c
1 1 1
Midway Bus

-681.3 [MW] A A MW_VT3_b

0.01
24.91 [MVAR]
Midway Line - Diablo Canyon 3 1
COUPLED
I63 B C

R63 V63
Fault_Loc_IB5
PI
SECTION Fault_Loc_IB4 C B DB_MW_f3
C A A
Timed
Breaker Midway Line - Diablo Canyon 3
Logic R63
Closed@t0

0.01
MW_VT3_b MW_VT3_c MW_VT3_c
V
V63

I
Metering
Page
Inst Xfmrs
P63 P63
B C C
I63 Q63 Q63

-685.3 [MW]

T-Lines
A A
183.1 [MVAR]
Midway Line - Diablo Canyon 2 1
COUPLED
I64 B C

R64 V64 PI
Fault_Loc_IB5 Fault_Loc_IB4 SECTION C B DB_MW_f2

Timed
Breaker R64
Timed
BRKR

Logic
Closed@t0
Breaker
Logic
BRKR
Closed@t0
V
V64 P64
4.062

P64 Line Reactor

Metering
I
Page
I64 Q64 Q64
Inst Xfmrs
B
MW3 Rec.
3
2
1

R64
1422 [MW]
Unit # 11
-427 [MVAR]
MIdway - Gates Line mov mov

I61

V61
R61
C C
R61T1

42-R61
C O R61 T1 FLTen 1000000.0 0.00326T
42-R61 R61
R61T2
sec

sec

Timed
Breaker
R61 T2 Logic
Closed@t0 V
GT
L
0 2 2 V61
Metering MW [Ctrl] FLTen
I FLTen
Page
I61 P61 P61
Inst Xfmrs
B V62
MW2 Rec. [Ctrl] FLTdetails

0.00326
1
2
3

3 Phase Q61 Q61

Fault
RMS MW-Vrms R61 1 1
Sequencer
FLTloc FE
1262 [MW] Control
2
-84.38 [MVAR]
MIdway - Gates Line mov mov FT

I62 6

Transformers
Ron
V62
R62
C C
1000000.0 T
Midw ay : Controls
R62T1

42-R62
C O L
R62 T1 FLTen
sec

sec

42-R62 R62
R62T2

Timed
Breaker
0 2 2 R62 T2 Logic
Closed@t0

0.00326
Manitoba HVDC Research Centre
V
V62
Metering PG&E Path 15 500kV Transmission
MW500

I
Page
I62
Inst Xfmrs
P62 P62 Line Protection System
MW230

MW500

B
MW1 Rec. Transient Studies
MW230

1
2
3

MW-ph Q62 Q62

1000000.0
Ph

R62
Dwg No. Rev Page T
RRL
Midway Source

PGE500 1 ?
F

Midway
L

Part of a 500kV station

60.0
230 kV
V

Connections
RL

MW-V

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 24

System data

The power system is modeled in detail with all frequency

dependent parameters when applicable.

VD-ph
Network boundary equivalences.
• Based on steady state fault levels
Ph
RRL

60.0
• Magnitude and phase externally
V

controlled from a master control page.

RL

VD-V This enables efficient data entry to

study many power flow situations.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 25

System data

The power system is modeled in detail with all frequency

dependent parameters when applicable.
Transformers
• Stray capacitances
modeled at buses near
the capacitor bank
station.
• Name plate and test
data sheets.
•Saturation data.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 26

System data

The power system is modeled in detail with all frequency

dependent parameters when applicable.

Mid-Span Sag:

12.19 [m] for Conductors

12.19 [m] for Ground Wires
Mid-Span Sag:

12.19 [m] for Conductors

12.19 [m] for Ground Wires
Transmission lines
• Tower geometry for
G1 G2
7.925 [m] G1 G2
12.496 [m] 7.925 [m]

frequency dependent
12.496 [m]
C1 C2 C3
C4 C5 C6
9.75 [m]

(bundling not exactly30.5 [m]

Tower: 3L1
9.75 [m]
models
• Bundling information.
as shown) Conductors: bluebird Tower: 3L1
(bundling not exactly30.5 [m]
Ground_Wires: 1/2"alumweld as shown) Conductors: bluebird

Ground_Wires: 1/2"alumweld

• Conductor data from

0 [m]
45.72 [m]

handbooks.
• Right of way information
Ground Resistivity: 100.0 [ohm*m]
Relative Ground Permeability: 1.0
Earth Return Formula: Analytical Approximation

and transposing.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 27

System data

The power system is modeled in detail with all frequency

dependent parameters when applicable.

Generators
• Modeled as voltage sources

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 28

System data

The power system is modeled in detail with all frequency

dependent parameters when applicable.
Segment 1 Segment 2

ZnO - MOV ZnO - MOV

ZnO - MOV ZnO - MOV

ZnO - MOV ZnO - MOV

Line compensation
• Capacitor stages.
0.5 5.0e-007 Ibpa11 0.01 0.5 5.0e-007 Ibpa12 Va1L
A Ia1m A A
Bp3a11 Va1m Bp3a12
0.5 5.0e-007 Ibpb11 0.01 0.5 5.0e-007 Ibpb12 Vb1L
B Ib1m B B
Bp3b11 Vb1m Bp3b12 Out
0.5 5.0e-007 Ibpc11 0.01 0.5 5.0e-007 Ibpc12 Vc1L
C Ic1m C C

• Protection.
Bp3c11 Vc1m Bp3c12

284.31 142.08

284.31 142.08

284.31 142.08
1000000.0

1000000.0

1000000.0

Reactors
• Saturable or linear

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 29

System data

The power system is modeled in detail with all frequency

dependent parameters when applicable.

a b c

Capacitor banks
• At all sub station in the
R1

C
A

Main Breaker

vicinity
• If there are low voltage
0.0023

0.0023

0.0023

Outrush Reactors

banks that might cause

resonance problems, the
network model may have to
CS01

CS02
C

C
A

Circuit switch Circuit switch

be extended.
0.0006

0.0006

0.0006

0.0006

0.0006

0.0006

Inrush Reactors Inrush Reactors

66 MVARS 66 MVARS
3.309

3.309

3.309

3.309

3.309

3.309

22 MVARs/Phase 22 MVARs/Phase

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 30

System data

The power system is modeled in detail with all frequency

dependent parameters when applicable.

Breakers
• individual pole closing
• Statistical switching.
• Pre insertion.
• Synchronized switching.
Statistical pole closing

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 31

System data

The power system is modeled in detail with all frequency

dependent parameters when applicable.
0.00075

Reactor
Inrush

MOVs
25 MVars per phase/step

• Non linear characteristics

• Manufacturers data sheets
Capacitor
3.76

• Rated voltage, MCOV

Rated Voltage

230 2
Vr  Vr  187.794
3

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 32

 Model validation

A very important step in a larger network model.

Frequency dependent line entries.

•PSCAD gives the positive, negative and zero
sequence impedance values. These can
be compared with load flow data.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 33

Model validation

The full model was validated with the following

methods.

1. Load flow
2. Fault level
3. Fault recordings

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 34

Model validation

Load Flow validation

• Checked for all lines
• Acceptable differences
• Some issues

LF PSCAD Diff LF PSCAD Diff

LB -372 -345 -27 -101 -55 -46
LB -797 -866 69 39 -40 79
DBL -134 -145 11 -20 5 -25
MDW 1195 1215 -20 69 12 57
total -108 -141 33 -13 -78 65

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 35

 Model validation

Fault level validation

• Checked at all substations
• Some issues
• Dc offset, harmonics

3LG(Amp) 2LG(Amp) - Phases A-B 1LG(Amp) Phase A 2LG(Amp) Phases A-B

ASPE PSCA ASPE PSCA ASPE PSCA

N D DIFF ASPEN PSCAD DIFF N D DIFF N D DIFF

22000 22000 0% 18000 19500 8% 20500 20000 2% 15000 15000 0%

27500 27000 2% 25000 26000 4% 21500 21000 2% 23500 23500 0%

30500 31500 3% 28500 29500 4% 22500 21500 4% 25500 27000 6%

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 36

Model validation

Fault recordings

Analog Graph
Near the fault bus A dvanced Graph Frame

DM2 IA Ias4
4.0k
MV1 EA Vas5
600.000k
3.0k
400.000k
2.0k
200.000k
1.0k
bus voltage

0.000

line #2
-200.000k 0.0

-400.000k -1.0k

-600.000k -2.0k

-800.000k

MV1 EB Vcs5
Voltages -3.0k

1.5k
DM2 IB Ics4
Currents
600.000k
1.0k
400.000k
0.5k
200.000k
bus voltage

0.0
0.000

line #2
-0.5k
-200.000k
-1.0k
-400.000k
-1.5k
-600.000k
-2.0k
MV1 EC Vbs5 DM2 IC Ibs4
600.000k 1.5k

400.000k 1.0k

200.000k 0.5k
bus voltage

0.000 0.0
line #2

-200.000k -0.5k

-400.000k -1.0k

-600.000k -1.5k

x 0.150 0.175 0.200 0.225 0.250 0.275 0.300 0.325 0.350 ... -2.0k

... x 0.150 0.175 0.200 0.225 0.250 0.275 0.300 0.325 0.350 ...
...
... ...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 37

Model validation

Fault recordings

Analog Graph
Near the fault bus A dvanced Graph Frame

DM2 IA Ias4
4.0k
MV1 EA Vas5
600.000k
3.0k
400.000k
2.0k
200.000k
1.0k
bus voltage

0.000

line #2
-200.000k 0.0

-400.000k -1.0k

-600.000k -2.0k

-800.000k

MV1 EB Vcs5
Voltages -3.0k

1.5k
DM2 IB Ics4
Current
600.000k
1.0k
400.000k
0.5k
200.000k
bus voltage

0.0
0.000

line #2
-0.5k
-200.000k
-1.0k
-400.000k
-1.5k
-600.000k
-2.0k
MV1 EC Vbs5 DM2 IC Ibs4
600.000k 1.5k

400.000k 1.0k

200.000k 0.5k
bus voltage

0.000 0.0
line #2

-200.000k -0.5k

-400.000k -1.0k

-600.000k -1.5k

x 0.150 0.175 0.200 0.225 0.250 0.275 0.300 0.325 0.350 ... -2.0k

... x 0.150 0.175 0.200 0.225 0.250 0.275 0.300 0.325 0.350 ...
...
... ...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 38

 Model validation

Fault recordings
• The simulation shows
6.0k
MV 1 IA
Analog Graph

At a remote bus
Midw ay.Ias5
the same trends
4.0k

2.0k
MW-VT Line #1

0.0

-2.0k

-4.0k

-6.0k

-8.0k
Current • Not all conditions are known at
2.5k

2.0k
MV 1 IC

Voltages
Midw ay.Ibs5

the instant of the fault.

1.5k

1.0k

0.5k
• Load flow
MW-VT Line #1

0.0

• Point on wave
-0.5k

-1.0k

-1.5k

• Reactors / capacitors ON
-2.0k

-2.5k

MV 3 IC Midw ay.Ibs7
3.0k

2.0k

1.0k
or OFF
MW-VT Line #3

0.0

-1.0k

-2.0k

-3.0k

x 0.160 0.180 0.200 0.220 0.240 0.260 0.280 0.300 0.320 0.340 ...
...
...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 39

 The Study

1. Harmonic distortion problems.

• Check how the addition of new equipment
affect the impedance spectrum.
• Should be checked at different points.
• Use the Harmonic Impedance Component
from the PSCAD library to perform a
frequency scan of the network

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 40

 The Study

1. Harmonic distortion problems.

Positive sequence impedance

All different combinations of

capacitor banks should be
considered.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 41

 The Study

1. Harmonic distortion problems.

Positive sequence impedance

Identify possible harmonic

distortion problems.
• Transformers or other
non linear devices

Possible solutions
• Design inrush/outrush as
tuned filters, Delta
connection, ungrounded
star

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 42

The Study

2. Transient Overvoltage study (TOV)

a. Capacitor bank switching.

Malfunction of synchronized closing.
230 kV, 60 Hz
Equivalent Source

A
RRL
Vabs Vabr
B 150 km
RRL
TLine
Vbcs Vbcr
C
RRL
Vcas Vcar

Vabs
Brk_A

Brk_A

Brk_A

Vbcs
Brk_A A52a
Breaker Switching
Vcas
and Multi-Run
Brk_B A52b
2.006

2.006

2.006

Controls
Vabr
Brk_C A52c
Vbcr

Vcar

40 MVAR
CAPACITOR BANK

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 43

The Study

2. Transient Over voltage study (TOV)

a. Capacitor bank switching.

TOVs and effect of traveling waves. Model
long lines as full frequency dependent.
No reflections
Transmission line reflections
Reflections modeled
Transmission line reflections
Vabs Vbcs Vcas Vabs Vbcs Vcas
500 500

400 400

300 300

200 200

100 100
kV

kV
0 0

-100 -100

-200 -200

-300 -300

-400 -400
Time 0.720 0.730 0.740 0.750 0.760 0.770 0.780 0.790 0.800 ... Time ...
0.720 0.730 0.740 0.750 0.760 0.770 0.780 0.790 0.800
... ...
... ...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 44

The Study

2. Transient Over voltage study (TOV)

a. Capacitor bank switching.
• Batch mode simulation using multiple run.
• Run from a ‘snapshot’.
• Control breaker pole closing instant on the
cycle
• Record and analyze data

How many switching

points per cycle. ?

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 45

The Study

2. Transient Over voltage study (TOV)

a. Capacitor bank switching.
• Pre-strike of breaker poles

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 46

The Study

2. Transient Over voltage study (TOV)

a. Faults and fault clearance.
• Different fault types.
• Fault inception and duration.

Faults

Vabs Vbcs Vcas

400
kV

-400

Vabr Vbcr Vcar

600
400
200
0
-200
kV

-400
-600
-800

Time 0.960 0.980 1.000 1.020 1.040 1.060 1.080 1.100 1.120 ...
...
...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 47

The Study

2. Transient Over voltage study (TOV)

a. Capacitor breaker re-strike.
• Likely to be the situation for the MOV X Axis
XY Plot

Y Axis

sizing. VbusA Imov

• Position of the MOV.(at caps or 230 kV 2.0k

+y

bus) 1.0k

-x +x

• MOV characteristics (V(pu)-I(kA) curve.

0.0

-1.0k

-2.0k
-y
-2.00 -1.00 0.00 1.00 2.00

Aperture Width 0....

0.000s 0.100s Position 0.000

•IEEE standard # C.62.11.1999 deals with surge arresters.

•See manufacturers worksheets for worked examples on guides
for MOV selection.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 48

 The Study

2. Transient Over voltage study (TOV)

a. Capacitor breaker re-strike.
Lab #1 Output
Lab #1 Output
VbusA VbusB VBusC
2.00 Imov
0.3k
1.50 0.0
-0.3k
1.00

0.50 Bus voltage -0.5k

-0.8k MOV Current

Current
-1.0k
Voltage

0.00
-1.3k
-0.50
-1.5k
-1.00 -1.8k
-2.0k
-1.50
-2.3k
-2.00
0.000 0.020 0.040 0.060 0.080 0.100 ...
0.000 0.020 0.040 0.060 0.080 0.100 ... ...
... ...
...

Lab #1 Output Lab #1 Output

Ia Energy
2.0k

1.0k
Line Current 160
140
MOV Energy
0.0 120
100
-1.0k
Current

80
-2.0k
kJ

60
-3.0k
40
-4.0k
20
-5.0k 0

0.000 0.020 0.040 0.060 0.080 0.100 ... ...

0.000 0.020 0.040 0.060 0.080 0.100
... ...
... ...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 49

The Study

2. Transient Over voltage study (TOV)

c. Voltage magnification at lower voltage
capacitors
– How close the two resonances are?
– Amount of damping due to system loads and losses
– Instant of energization of the switched bank

1 1
BRK

0.1 0.1
L2 f1  f2 
L1 2 L1 C1 2  L2 C2
RRL

Bus voltage
1.0

1.0

C1 C2 IEEE Report # TP-133-0

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 50

The Study

2. Transient Over voltage study (TOV)

c. Voltage magnification at lower voltage
capacitors Bus voltage at low voltage caps Main : Graphs

Eas
1.3k
Timed
Breaker 1.0k
BRK
Logic
Open@t0 0.8k Caps ON
A
0.5k
0.003 0.0005 0.07
B 0.3k

y
0.0005 0.07
0.0
C
Eas Eas Cbrk -0.3k
0.0005 0.07 Eap

-0.5k
C
A

CPa... -0.8k
#2

Eap
BRK

11.0

Eap <Untitled>
C
A

0.100 [MVA]

OFF ON Eas
1.3k
0.415

1.0k
Caps OFF
#1
400.0

400.0

400.0
20.0

20.0

20.0

1
0.8k
C
A

B
Eas

cbrk 0.5k
A 320.0 0.3k

y
0.0
B 320.0
-0.3k
C 320.0
-0.5k
-0.8k
8.0

8.0

8.0

0.020 0.040 0.060 0.080 0.100 0.120 0.140 ...

...
...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 51

The Study

2. Transient Over voltage study (TOV)

d. Voltage magnification at open transformer
phase windings

IEEE Report # TP-133-0

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 52

The Study

2. Transient recovery voltage study (TRV)

To investigate the breaker compliance to
standards (IEEE standard # C.37.011.1994)

TRV – Voltage across the breaker poles when

interrupting a current.

If the TRV is too high, the arc interruption will be

unsuccessful and re-strike will occur.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 53

The Study

2. Transient recovery voltage study (TRV)

TRV Capability curve
• Complex
• Defined as exponential,triangular,cosine
etc.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 54

The Study

2. Transient recovery voltage study (TRV)

TRV Capability curve

Period of interest is in the s range ( 300 -1000)

Main : Graphs

emaxi TRV on
400

350
IEEE Standard #
300
C37.06.2000 list TRV
250

200
capability parameters.
kV

150

100
Curve rescaled
50

0
depending on % fault
-50

...
current being
0.0994 0.0996 0.0998 0.1000 0.1002 0.1004 0.1006 0.1008 0.1010 0.1012
...
... intrrupted.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 55

The Study

2. Transient recovery voltage study (TRV)

15.0
Ea
TRV Waveforms 20
TRV_ENV(+) TRV_ENV(-) Ea

10.0

10
5.0

0.0
0
-5.0

-10.0
-10
-15.0

-20.0
-20

-25.0

-30.0 -30

0.000 0.010 0.020 0.030 0.040 0.050 ... ...

0.021810 0.021820 0.021830 0.021840 0.021850 0.021860 0.021870 0.021880 0.021890 0.021900 0.021910
... ...
... ...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 56

The Study

2. Transient recovery voltage study (TRV)

Modeling issues:
• Low time step.
• Stray capacitance is important if the breaker is
not at the end of a long line.
• Grading capacitors.
• Worst TRV situations.
• 3-phase ungrounded fault.?

If the results are not conclusive, consult the manufacturer.!

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 57

 The Study

2. Dynamic over-voltage issues (DOV)

Ea
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50

Isec
0.80
0.60
0.40
0.20
0.00
-0.20
-0.40
-0.60

Ipri
0.150
0.100
0.050
0.000
-0.050
-0.100
-0.150

0.00 0.50 1.00 1.50 2.00 2.50 3.00 ...

...
...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 58

 The Study

• Harmonic Voltage distortion.

Ea Ea
20 20
10 10
0 0
-10 -10
-20 -20

Isec Isec
0.20 0.20
0.10 0.10
0.00 0.00
-0.10 -0.10
-0.20 -0.20

If l If l
0.020 0.020
0.010 0.010
0.000 0.000
-0.010 -0.010
-0.020 -0.020

Ipri Ipri

0.050 0.050

0.000
Without filter 0.000 With filter
-0.050 -0.050

0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.070 0.080 0.090 0.100 ... 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.070 0.080 0.090 0.100 ...
... ...
... ...

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 59

 Conclusions from the study

• Design inrush and outrush reactros.

• Identify possible harmonic distortion problems.
• Determine the ratings of the MOV.
• Select a suitable breaker and verify its operation under
different conditions.
• Identify voltage magnification problems.

The existing breakers, MOV’s etc. in the visinity of the

new capacitor bank may also have to be revisited.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 60

 Conclusions

• How to set up a simulation case for a switching study.

• Modeling different components.
• Network boundaries
• Validation
• Performing a switching study.
• Relevant standards.
• TOV
• TRV
• Harmonic distortion
• Amplification

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 61

 Conclusions

• Models available in PSCAD to aid such a study

• Multiple-run.
• Control blocks
• Data transmitters
• Page modules

• PSCAD simulation cases.

• Simple cases are provided for reference. Some
cases may not run on the student edition.

July 3, 2019 Case Study - Capacitor Bank Switching Transients Page 62