Scribd
Upload
107 views16 pages

Unit-Viii: Arm 32-Bit Mcus: Architecture, Programming, & Development Tools

ARM 32-bit MCUs have a 32-bit instruction set and 16-bit compressed Thumb instruction set, making them 16/32-bit processors. They use pipeline processing for high performance at low power. ARM designs RISC superscalar processors for implementation in VLSI. There are variants of the ARM architecture for different applications and features. ARM MCUs come from several manufacturers and are used widely in embedded systems.

Uploaded by

virikris
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
107 views16 pages

Unit-Viii: Arm 32-Bit Mcus: Architecture, Programming, & Development Tools

ARM 32-bit MCUs have a 32-bit instruction set and 16-bit compressed Thumb instruction set, making them 16/32-bit processors. They use pipeline processing for high performance at low power. ARM designs RISC superscalar processors for implementation in VLSI. There are variants of the ARM architecture for different applications and features. ARM MCUs come from several manufacturers and are used widely in embedded systems.

Uploaded by

virikris
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 16

Unit- VIII

ARM 32-bit MCUs:


Architecture,
Programming, &
Development tools
Introduction to 16/32 bit Processors
• ES need Precise computing, Minimum
Power dissipation at high speed
computations & smaller code-size
• These features can be provided by 32-bit ARM
& 16-bit Thumb instruction set
• ARM is highly valuable for applications like
mobile phones, image processing, video
games, robotics & adaptive control systems
• ARM has 32-bit instruction set supported by a
16-bit compressed code, called Thumb
instruction set and is called 16/32-bit
processor
• Superscalar processor has pipeline for
processing in which more than one instruction
is fetching, decoding & executing
• The performance becomes n-times in n-stage
pipeline in superscalar processor .
• Pipeline gives n-times greater performance in
MIPS for same clock speed & same
architecture implementation
• ARM stands for Advance RISC Machines who
designed a family of RISC superscalar
processor architecture for VLSI
implementation
• ARM VLSI are widely as a core or chip .
• Registered TM of ARM Limited
• Offers high performance at very low power
consumption
ARM Processor features & variants
Superscalar Processor pipeline feature shown by three stage
pipeline in ARM –family of processors
ARM Architecture & Organization

• Have following variants of architecture


• (a) v1-ARM1,v2-ARM2,v2as-ARM3 & ARM250,v3-full 32-bit addressing for
both data & code ARM6,ARM7,ARM8 and Amulet 1, v3M- ARM6,ARM7 &
ARM8, v4-strongARM,ARM9, v5-ARM10,VFP1-ARM10 for floating point
performance on typical graphics & DSP algorithm
• (b) Thumb (T variants)
• (c) Long multiply instructions
• (d) Enhanced DSP instructions (E variants)
• Features:
• 0.25-µm, less Die size, HCMOS , low power & voltage
• High performance of 300 MIPS
• Fully static operation
• 16 32-bit registers
• 3 stage pipeline
• 232 addresses for 4GB linear address space
• 32/16 RISC architecture
• 2-bit RALU & high performance multiplier
• Common internal bus for data & address
• Instruction process data with 8,16 ,32-bit data types
• FIQ & IRQ
• Co-processor interface
• ARM memory interface has speed-critical control signals
• Extensive debug facilitates RT debug & on-chip JTAG
• Interface for direct connection to embedded trace macro cell
(ETM)
ARM based MCUs

• ARM MCUs are from several sources


• ARM7TDMI – ST Microelectronics ARM based MCU
chips
• it has high end 32-bit single-VLSI MCUs
• Atmel manufactures AT91 single chip controller .
• It has CAN (stands for controller area network bus used
for networking the embedded controllers)
• ARM based low cost & high performance Philips MCUs
are low power LPC2114 & LPC2124
• ARM based MCU S3C2410x01 is manufactured by
Samsung (widely used in Pocket PC & PDA)
ARM/Thumb Programming model
• Overview of ARM-Family MCU
• ARM7 (Princeton), ARM 9 (Harvard Architecture)
• ARM 16/32-bit RISC .Processor can operate on 32-
bit word at an instance & can also operate separately
on each byte of a word ,byte0,1,2,3.
• Word alignment can be big endian & little endian
• Princeton architecture makes reuse of instruction
• High performance computating
CPU Programming model of Registers, address and
data buses, & interrupts
• ARM processor has a distinct programming model . It
characterizes by a large set of 16 general purpose registers.
• Program counter , CPSR (current program status register )&
SPSR (saved program status register )
• An Instruction set characteristics are as follows
• (1) Addressing modes
• (2) Instruction types
• (3) Number of operands in the instruction
• (4) Instructions of fixed length or variable lengths
Overview of CPU Architecture
• ARM 7 & 9 supports 300MIPS ,16 32-bit registers (r0
to r5) form general purpose registers (GPR) set
• RALU does Add, Subtract, reverse subtract, multiply,
MWA. It has a barrel shifter
• GPR can function for computations
• 32/16-bit ARM instruction set feature is Load & store
architecture
• 32 bit memory space
• 2 modes of processor- user mode & supervisory
mode
• SWI handler is used for passing the parameter &
interrupt number .RISC OS uses SWI. IHR
ARM/Thumb Instruction Set
• 32/16-bit ARM Instruction set:
• Register addressing
• Immediate Addressing
• Indirect Base and Indexed Addressing
• (a) A byte or half-word or word address is pointed by the indirect
address in GPR
• (b) A byte or half-word or word address is pointed by the indirect
address obtained by subtracting 2 registers of GPR set
• (c) A byte or half-word or word address is pointed by the indirect
address by the indirect base address by adding GPR with an offset as
immediate operand
• (d) There is an indirect addressing mode by index plus offset with post
auto indexing
• (f) There is an indirect addressing mode by index plus offset with pre-
auto indexing by using an operator

You might also like