CONTENTS
• Project Flow
• Introduction
• UART Design
• Baud Rate Generator
• Transmitter
• Receiver
• Block diagram of UART
• Simulation Result
• RTL Schematic
• Technology Schematic
• Reports
• Conclusion
• Future Work
• References
Project Flow
Literature Survey.
Design of Baud rate generator.
Design of receiver and transmitter.
Debugging of UART.
Simulation.
Synthesis.
Verification.
Implementation.
Introduction
UART acronym for Universal Asynchronous
Receiver and Transmitter.
Asynchronous Serial communication protocol.
Full Duplex communication.
Used between the slow and the fast peripheral
devices.
Contd..
Converts the bytes it gets from the computer along
parallel circuits to a single serial bit stream for
outbound transmission.
For inbound transmission, converts the serial bit
stream to the bytes that the system handles.
Adds a parity bit after selection in outbound
transmissions, checks the parity of incoming bytes (if
selected) and rejects the parity bit.
UART Design
A UART frame consists of 1 start bit, a number of
data bits, an optional parity bit and 1, 1.5, or 2 stop
bits.
Signal is 1 (high voltage) when the system is idle.
Start bit is 0 and stop bits are 1.
LSB is first transmitted or received.
Contd..
UART is composed of a Baud Rate Generator
(BRG), a receiver module, and a transmitter module
Designed by using Modular design approach.
Baud Rate Generator
Baud rate: The number of bits transmitted per
second. frequently used baud rate: 9600, 19,200.
𝑓𝑐𝑙𝑘
n=
𝐵𝑚𝑎𝑥 ×𝐶×2
Where
fclk: system clock Frequency
C: the number of samples per bit cell
Brmax: the maximum baud rate frequency
Contd..
Multiplexer based designing of baud rate
generator is used.
RTL Code of Baud Rate generator
Clock divide by n Divide by 256
module clk_div(input clk,rst, module counter_8(input clk,rst,
output q) output reg [7:0]q);
reg [2:0]q1;
always@(posedge clk)
always@(posedge clk) begin
begin if(!rst) if(!rst)
q1<=3'b001; q<=8'd0;
else else
q<=q+1;
q1<={q1[0],q1[2:1]};
end
end endmodule
assign q=q1[0];
endmodule
Contd..
Multiplexer Divide by 8
module mux_8(input [7:0]d, module divide_by_8(input clk,rst,
input [2:0]sel, output q);
output reg y); reg [2:0]count;
always@(d,sel)
always@(posedge clk,negedge rst)
begin case(sel)
begin
3'b000:y=d[0];
3'b001:y=d[1]; if(!rst)
3'b010:y=d[2]; count<=3'd0;
3'b011:y=d[3];
3'b100:y=d[4];
else
3'b101:y=d[5]; count<=count+1;
3'b110:y=d[6]; end
3'b111:y=d[7]; assign q=count[2];
endcase
endmodule
end
endmodule
Block Diagram of Transmitter
Logic diagram of the transmitter of a UART.
1
1 P 0 TxD
Parity generator
TE
TxC Transmitter Control TDR
Data Bus
SM of Transmitter
bct=10
Block Diagram of Receiver
Logic diagram of the receiver of UART
DATA BUS
RDR FE OE PE RF RcvSR
RxD RxC
1 P RSR 0 Receiver Control
SM of Receiver
Block Diagram
SIMULATION RESULTS
Simulation result of baud
rate generator
Contd..
Simulation result of UART
RTL SCHEMATIC
Technology Schematic
POST SYNTHESIS UTILIZATION REPORT
POST IMPLEMENTATION UTILIZATION
REPORT
Power report
There are 2 power report.
• Post synthesis
• Post route
Two modes of power estimation
• Vector based
• Vector less
POST SYNTHESIS POWER REPORT
POST IMPLEMENTATION POWER
REPORT
Conclusion
UART Module is designed by using Verilog HDL.
Design is simulated and verified with the help of
output waveform in Xilinx Vivado HLS.
The design code if fully synthesizable and has no
latch.
Future Work
Verification of UART.
Implementation on FPGA.
REFERENCES
U. Nanda and S. K. Pattnaik, “Universal asynchronous receiver
and transmitter (uart),” in Advanced Computing and
Communication Systems (ICACCS), 2016 3rd International
Conference on, vol. 1. IEEE, 2016,pp. 1–5.
Y.-y. Fang and X.-j. Chen, “Design and simulation of uart serial
communication module based on vhdl,” in Intelligent Systems and
Applications (ISA), 2011 3rd International Workshop on. IEEE,
2011, pp. 1–4.
G. B. Wakhle, I. Aggarwal, and S. Gaba, “Synthesis and
implementation of uart using vhdl codes,” in Computer, Consumer
and Control (IS3C), 2012 International Symposium on. IEEE, 2012,
pp. 1–3.
Y. Wang, and K. Song, “A new approach to realize UART,” Int’l
Conf. on Elect. and Mech. Eng. and IT (EMEIT 2011), Harbin,
Heilongjiang, China, Aug. 2011.
