Verilog HDL

Gate-Level Modeling

Sujay S N
Asst. Prof.
Dept. of ECE
Dr. AIT, Bangalore
Learning Objectives

• Identify logic gate primitives provided in Verilog.

• Understand instantiation of gates, gate symbols, and truth

tables for and/or and buf/not type gates.

• Understand how to construct a Verilog description from the

logic diagram of the circuit.

• Describe rise, fall, and turn-off delays in the gate-level design.

• Explain min, max, and typ delays in the gate-level design.

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Gate Types

• There are two classes of basic gates: and/or gates and buf/not
gates.

And/Or Gates
• The first terminal in the list of gate terminals is an output and
the other terminals are inputs
• The and/or gates available in Verilog are shown below.

and or xor nand nor xnor

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•These gates are instantiated to build logic circuits in Verilog
•More than two inputs can be specified in a gate instantiation.
•Gates with more than two inputs are instantiated by simply
adding more input ports in the gate instantiation.
•Verilog automatically instantiates the appropriate gate.

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Gate Instantiation of And/Or Gates

wire OUT, IN1, IN2;

// basic gate instantiations.

and a1(OUT, IN1, IN2);
nand na1(OUT, IN1, IN2);
or or1(OUT, IN1, IN2);
nor nor1(OUT, IN1, IN2);
xor x1(OUT, IN1, IN2);
xnor nx1(OUT, IN1, IN2);

// More than two inputs; 3 input nand gate

nand na1_3inp(OUT, IN1, IN2, IN3);

// gate instantiation without instance name

and (OUT, IN1, IN2); // legal gate instantiation

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Buf/Not Gates
Two basic buf/not gate primitives are provided in Verilog.

buf not

Gate Instantiations of Buf/Not Gates

// basic gate instantiations.
buf b1(OUT1, IN);
not n1(OUT1, IN);

// More than two outputs

buf b1_2out(OUT1, OUT2, IN);

// gate instantiation without instance name

not (OUT1, IN); // legal gate instantiation
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Bufif/notif
Gates with an additional control signal on buf and not gates are also
available.

bufif1 notif1 bufif0 notif0

•These gates propagate only if their control signal is asserted.

•They propagate z if their control signal is deasserted

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Gate Instantiations of Bufif/Notif Gates

//Instantiation of bufif gates.

bufif1 b1 (out, in, ctrl);
bufif0 b0 (out, in, ctrl);

//Instantiation of notif gates

notif1 n1 (out, in, ctrl);
notif0 n0 (out, in, ctrl);

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Array of Instances
•There are many situations when repetitive instances are
required.
•These instances differ from each other only by the index of the
vector to which they are connected.

Simple Array of Primitive Instances

wire [7:0] OUT, IN1, IN2;

// basic gate instantiations.

nand n_gate[7:0](OUT, IN1, IN2);

// This is equivalent to the following 8 instantiations

nand n_gate0(OUT[0], IN1[0], IN2[0]);
nand n_gate1(OUT[1], IN1[1], IN2[1]);
nand n_gate2(OUT[2], IN1[2], IN2[2]);
nand n_gate3(OUT[3], IN1[3], IN2[3]);
nand n_gate4(OUT[4], IN1[4], IN2[4]);
nand n_gate5(OUT[5], IN1[5], IN2[5]);
nand n_gate6(OUT[6], IN1[6], IN2[6]);
nand n_gate7(OUT[7], IN1[7], IN2[7]);
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Examples

4-to-1 Multiplexer

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Logic Diagram for Multiplexer

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// Module 4-to-1 multiplexer. Port list is taken exactly from the I/O
diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
// Internal wire declarations
wire s1n, s0n;
wire y0, y1, y2, y3;

// Gate instantiations
// Create s1n and s0n signals.
not n1(s1n, s1);
not n2(s0n, s0);

// 3-input and gates instantiated

and a1(y0, i0, s1n, s0n);
and a2(y1, i1, s1n, s0);
and a3(y2, i2, s1, s0n);
and a4(y3, i3, s1, s0);

// 4-input or gate instantiated

or o1(out, y0, y1, y2, y3); 12
endmodule
 Stimulus for Multiplexer
// Define the stimulus module (no ports)
module stimulus;

// Declare variables to be connected to inputs

reg IN0, IN1, IN2, IN3;
reg S1, S0;

// Declare output wire

wire OUTPUT;

// Instantiate the multiplexer

mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

// Stimulate the inputs

// Define the stimulus module (no ports)
initial
begin
// set input lines
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n", IN0, IN1, IN2, IN3);

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// choose IN0
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN1
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN2
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end

endmodule

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The output of the simulation is shown below

IN0= 1, IN1= 0, IN2= 1, IN3= 0

S1 = 0, S0 = 0, OUTPUT = 1

S1 = 0, S0 = 1, OUTPUT = 0

S1 = 1, S0 = 0, OUTPUT = 1

S1 = 1, S0 = 1, OUTPUT = 0

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4-bit Ripple Carry Full Adder

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OR

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// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);

// I/O port declarations

output sum, c_out;
input a, b, c_in;

// Internal nets
wire s1, c1, c2;

// Instantiate logic gate primitives

xor (s1, a, b);

and (c1, a, b);

xor (sum, s1, c_in);

and (c2, s1, c_in);

xor (c_out, c2, c1);

endmodule
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// Define a 4-bit full adder
module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations

output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;

// Internal nets
wire c1, c2, c3;

// Instantiate four 1-bit full adders.

fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);

endmodule

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Stimulus for 4-bit Ripple Carry Full Adder
// Define the stimulus (top level module)
module stimulus;

// Set up variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Instantiate the 4-bit full adder. call it FA1_4

fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);

// Set up the monitoring for the signal values

initial
begin
$monitor($time," A= %b, B=%b, C_IN= %b, C_OUT= %b, SUM= %b\n",
A, B, C_IN, C_OUT, SUM);
end

// Stimulate inputs
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initial
begin
A = 4'd0; B = 4'd0; C_IN = 1'b0;

#5 A = 4'd3; B = 4'd4;

#5 A = 4'd2; B = 4'd5;

#5 A = 4'd9; B = 4'd9;

#5 A = 4'd10; B = 4'd15;

#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;

end

endmodule

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Gate Delays

In real circuits, logic gates have delays associated with them.

Rise, Fall, and Turn-off Delays

The rise delay is associated with a gate output transition to a 1 from
another value.

The fall delay is associated with a gate output transition to a 0 from

another value.

The turn-off delay is associated with a gate output transition to the

high impedance value (z) from another value.

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If the value changes to x, the minimum of the three delays is
considered.

Three types of delay specifications are allowed.

If only one delay is specified, this value is used for all transitions.

// Delay of delay_time for all transitions

and #(delay_time) a1(out, i1, i2);

If two delays are specified, they refer to the rise and fall delay
values. The turn-off delay is the minimum of the two delays.

// Rise and Fall Delay Specification.

and #(rise_val, fall_val) a2(out, i1, i2);

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If all three delays are specified, they refer to rise, fall, and
turn-off delay values.

// Rise, Fall, and Turn-off Delay Specification

bufif0 #(rise_val, fall_val, turnoff_val) b1 (out, in, control);

If no delays are specified, the default value is zero.

Examples of delay specification

and #(5) a1(out, i1, i2); //Delay of 5 for all transitions

and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6
bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3, Fall = 4, Turn-off= 5

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Min/Typ/Max Values

 Verilog provides an additional level of control for each type of delay

 For each type of delay rise, fall, and turn-off, three values
min, typ and max, can be specified.

 Whose delays vary within a minimum and maximum range

because of the IC fabrication process variations.

 The min value is the minimum delay value that the designer
expects the gate to have.
 The typ value is the typical delay value that the designer expects
the gate to have.
 The max value is the maximum delay value that the designer
expects the gate to have.

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Min, typ, or max values can be chosen at Verilog run time.

Method of choosing a min/typ/max value may vary for different

simulators or operating systems.

(For Verilog- XL , the values are chosen by specifying options

+maxdelays, +typdelays, and +mindelays at run time. If no option is
specified, the typical delay value is the default).

This allows the designers the flexibility of building three delay values
for each transition into their design.

The designer can experiment with delay values without modifying

the design.

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Example : Min, Max, and Typical Delay Values

// One delay
// if +mindelays, delay= 4
// if +typdelays, delay= 5
// if +maxdelays, delay= 6
and #(4:5:6) a1(out, i1, i2);

// Two delays
// if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)
// if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)
// if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)
and #(3:4:5, 5:6:7) a2(out, i1, i2);

// Three delays
// if +mindelays, rise= 2 fall= 3 turn-off = 4
// if +typdelays, rise= 3 fall= 4 turn-off = 5
// if +maxdelays, rise= 4 fall= 5 turn-off = 6
and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2);

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Examples of invoking the Verilog-XL simulator with the command-
line options are shown below.
Assume that the module with delays is declared in the file test.v.

//invoke simulation with maximum delay

> verilog test.v +maxdelays
//invoke simulation with minimum delay
> verilog test.v +mindelays
//invoke simulation with typical delay
> verilog test.v +typdelays

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Delay Example

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