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Modelsim: VHDL & Verilog Simulator

Modelsim is a VHDL and Verilog simulator. It requires changing the directory to where design files exist, creating a work library for the design, and compiling source files. After compilation, the top-level module is loaded for simulation. Signals can then be added to the waveform analyzer and the simulator run to see simulation results and verify the circuit behavior.

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0% found this document useful (0 votes)

22 views

Modelsim: VHDL & Verilog Simulator

Uploaded by

lbhanu408

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PPT, PDF, TXT or read online on Scribd

You are on page 1/ 16

Modelsim

VHDL & Verilog Simulator.

1
Modelsim

Change the directory to where your files exist (All of

the files must be in a same folder). 2
Modelsim

Create a work library for your design which

contains design compile information. 3
Modelsim

Create the library through this dialog box.

4
Modelsim

You can see all information about your design by

selecting All item from View menu.
5
Modelsim

6
Modelsim

First, compile your source files.

7
Modelsim

Choose what file should be compiled.

8
Modelsim

After successful compilation, load your design.

9
Modelsim

Select the design’s top-level module (i.e. test

bench) to be loaded. 10
Modelsim

After successful loading…

11
Modelsim

Add signals in the module’s region to the waveform

analyzer. 12
Modelsim

Run the simulator to simulate the described

circuit. 13
Modelsim

See and verify your simulation results.

14
Modelsim

You can change the radix of the waveforms.

15
Modelsim

Also, You can change the color of waveforms.

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Modelsim: VHDL & Verilog Simulator

Uploaded by

Modelsim: VHDL & Verilog Simulator

Uploaded by

Modelsim

VHDL & Verilog Simulator.

Change the directory to where your files exist (All of

Create a work library for your design which

Create the library through this dialog box.

You can see all information about your design by

First, compile your source files.

Choose what file should be compiled.

After successful compilation, load your design.

Select the design’s top-level module (i.e. test

After successful loading…

Add signals in the module’s region to the waveform

Run the simulator to simulate the described

See and verify your simulation results.

You can change the radix of the waveforms.

Also, You can change the color of waveforms.

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