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Testing of VLSI Circuits

The document discusses concepts in VLSI design and testing including fault models, automatic test equipment, logic simulation, the VLSI realization process from customer requirements to chips to customers, definitions of design synthesis and verification, real tests and their limitations in yielding and defect level, the VLSI testing process and equipment, fault models for testing and verification such as stuck-at and delay, and an overview of VLSI testing in three phases from design verification to manufacturing tests to field testing.

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jeyapriya
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141 views

Testing of VLSI Circuits

The document discusses concepts in VLSI design and testing including fault models, automatic test equipment, logic simulation, the VLSI realization process from customer requirements to chips to customers, definitions of design synthesis and verification, real tests and their limitations in yielding and defect level, the VLSI testing process and equipment, fault models for testing and verification such as stuck-at and delay, and an overview of VLSI testing in three phases from design verification to manufacturing tests to field testing.

Uploaded by

jeyapriya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Concepts in VLSI Design

• Definition of Testing

• Fault Models

• Automatic Test Equipment

• Logic Simulation

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VLSI Realization Process

Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification

Test development

Fabrication

Manufacturing test

Chips to customer

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Definitions
• Design synthesis: Given an I/O function,
develop a procedure to manufacture a device
using known materials and processes.
• Verification: Predictive analysis to ensure that
the synthesized design, when manufactured, will
perform the given I/O function.
• Test: A manufacturing step that ensures that the
physical device, manufactured from the
synthesized design, has no manufacturing
defect.
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Real Tests
• Based on analyzable fault models.
• Incomplete coverage of modeled faults
due to high complexity.
• Some good chips are rejected. The
fraction (or percentage) of such chips is
called the yield loss.
• Some bad chips pass tests. The fraction
(or percentage) of bad chips among all
passing chips is called the defect level.

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VLSI Testing Process and Equipment

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Testing and Verification
• Faults models
– Stuck-at
– Delay
– Bridging
• Test pattern generation
• Built-in Self-Test (BIST)
• Space and Time Compaction
• Design for Testability (DFT)
• Synthesis for Testability (SFT)
• Low-power Testing
• Verification and simulation
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VLSI Testing
 What is VLSI testing?
– VLSI testing is to test the behavioral correctness of
a VLSI design.
– Three Phases:
 Design verification involves ascertaining logical
correctness and timing behavior of the circuit
through simulation.
 Manufacturing tests check for the specific types
of defects produced during fabrication.
 Field test (day-to-day testing).

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Testing Principle

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