Algorithms for VLSI Design

Automation

Instructor D. Zhou
[email protected]
Phone: 972 883 4392
Office: ECN 4.610
 Outline
History and the road map
Traditional design flow
Physical design fundamentals
Performance issues
System on chip

21/12/7 Dragon Star Shot Course 2

 History and the road map
The history of IC
 The invention of transistor
 The invention of integrated circuit
 IC has changed our life
Moore’s Law
 IC performance and complexity have been
doubled in every two years
Road Map

21/12/7 Dragon Star Shot Course 3

 The invention of transistor
John Bardeen, Walter Brattain & Wiliam
Shockley in vented “The first transistor”
in 1947.

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 The invention of integrated circuit
Jack Kilby & Robert Noyce inveted “The
Integrated Circuit” in 1958.

21/12/7 Dragon Star Shot Course 5

 Moore’s Law
 In 1965, Gordon Moore predicted that the number of tra
nsistors that can be integrated on a die would double e
very 18 to 14 months (i.e., grow exponentially with tim
e).
 Amazingly visionary – million transistor/chip barrier was
crossed in the 1980’s.
 2300 transistors, 1 MHz clock (Intel 4004) - 1971
 16 Million transistors (Ultra Sparc III)
 42 Million, 2 GHz clock (Intel P4) - 2001
 140 Million transistor (HP PA-8500)

CSE477 L01 Introduction.6 Irwin&Vijay, PSU, 2002

 Intel 4004 Microprocessor

CSE477 L01 Introduction.7 Irwin&Vijay, PSU, 2002

 Intel Pentium (IV) Microprocessor

CSE477 L01 Introduction.8 Irwin&Vijay, PSU, 2002

 Moore’s Law in Microprocessors
Transistors on lead microprocessors double every 2 years

1000

100 2X growth in 1.96 years!

Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
CSE477 L01 Introduction.9 Courtesy, Intel Irwin&Vijay, PSU, 2002
 Evolution in DRAM Chip Capacity
human memory
100000000
human DNA
64,000,000

10000000
4X growth every 3 years! 16,000,000 0.07 m
4,000,000
0.1 m
1000000 1,000,000
0.13 m
256,000
Kbit capacity/chip

book 0.18-0.25 m
100000
64,000
0.35-0.4 m
16,000
10000 0.5-0.6 m
4,000 encyclopedia
0.7-0.8 m
1000 1,000 2 hrs CD audio
1.0-1.2 m 30 sec HDTV
256
100 1.6-2.4 m
64
page
10
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year
CSE477 L01 Introduction.10 Irwin&Vijay, PSU, 2002
 Die Size Growth

Die size grows by 14% to satisfy Moore’s Law

100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year
CSE477 L01 Introduction.11 Courtesy, Intel Irwin&Vijay, PSU, 2002
 Clock Frequency

Lead microprocessors frequency doubles every 2 years

10000

1000 2X every 2 years

Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
CSE477 L01 Introduction.12 Courtesy, Intel Irwin&Vijay, PSU, 2002
 Power Dissipation

Lead Microprocessors power continues to increase

100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Power delivery and dissipation will be prohibitive

CSE477 L01 Introduction.13 Courtesy, Intel Irwin&Vijay, PSU, 2002

 Power Density
10000
Rocket
Nozzle
Power Density (W/cm2)

1000

Nuclear
100 Reactor

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

CSE477 L01 Introduction.14 Courtesy, Intel Irwin&Vijay, PSU, 2002

 Technology Trend
International Technology Roadmap
for Semiconductors (ITRS)

Production year 2002 2003 2004 2005 2006 2007

MPU Gate length 75 65 53 45 40 35
(nm)
Clock (GHz) 2.3 3.1 4.0 5.2 5.6 6.7
Metal layers 8 8 8 9 9 9
Supply voltage (V) 1.0 1.0 1.0 0.9 0.9 0.7

Microelectronics
MicroelectronicsDepartment,
Department,Fudan
FudanUniversity
University
 Traditional design flow
Traditional design flow (see slides design-
flow)
What has not been addressed in depth
 Understand application
 Architecture synthesis
 Verification is not complete

21/12/7 Dragon Star Shot Course 16

21/12/7 Dragon Star Shot Course 17
Microelectronics
MicroelectronicsDepartment,
Department,Fudan
FudanUniversity
University
 Performance issues
Speed
Noise
Clock distribution
Power distribution
Low power

21/12/7 Dragon Star Shot Course 19

 SOC
A low cost solution
Challenges
 Modeling
 Simulation
 Mixed signal
 Different processing
 Timing

21/12/7 Dragon Star Shot Course 20

 Agenda
Dealing with technology
 Masks
 Front-end manufacturing
 Back-end manufacturing
Application requirements
Putting it all together

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 Agenda
Dealing with technology
 Masks
 Front-end manufacturing
 Back-end manufacturing
Application requirements
Putting it all together

21/12/7 Dragon Star Shot Course 22

 Semiconductor Process Flow
Systems $1050B EDA $3.6B Masks $2.8B
Design Mask Data • Manufacturing $2.3B
• Computers • Tools $0.5B
• Communications EDA $2.7B
Comp Platforms Masks
• Consumer
• Industrial, Military…
Embedded SW $0.8B Front-End Manufacturing $24B
IP $0.9B • Process Auto $1B
• Lithography $6B
Semiconductors $119B • Etch/Doping $6B
• Micros, DSP $45B • Diffusion $1B
• Memory $25B • Deposition $5B
• ASIC, ASSP $25B • Other (CMP, Ion,
Wafer $4B Photoresist, etc.) $5B
• Analog, Discrete $25B
Back-End Manufacturing $6B
• Bonding $1B
• Packaging $2B
Chips • Test equipment $3B

21/12/7 Market size for 2001 Sources: Thomas Weisel Dataquest,

Dragon ICI, Star
Synopsys
ShotEstimates
Course 23
 Exploding Mask Costs
Year 1999 2002 2004 2007
Node .18µm .13µm .9µm .065µm
Cost $200-400K $500K-1M $800K-1.2M $1-2M
Data 16GB 64GB 256GB 1024GB

Raster scan patterning exposure time for a 110mm x 110 mm

mask is 6.5 hrs and 20 hrs with fine granularities (60nm vs. 120nm
pixel size)
Largest cost contribution to mask making is mask exposure time
(capital cost ~$20M)
RET is being absorbed by CAD vendors into layout verification /
tape-out suites.
RET may move up into routing, placement

21/12/7
Source: Thomas Weisel Partners Dragon Star Shot Course 24
 Front-End Processing
Systems $1050B EDA $3.6B Masks $2.8B
Design Mask Data • Manufacturing $2.3B
• Computers • Tools $0.5B
• Communications EDA $2.7B
Masks
• Consumer Comp Platforms
• Industrial, Military…
Embedded SW $0.8B Front-End Manufacturing $24B
IP $0.9B • Process Auto $1B
• Lithography $6B
Semiconductors $119B • Etch/Doping $6B
• Micros, DSP $45B • Diffusion $1B
• Memory $25B • Deposition $5B
• ASIC, ASSP $25B • Other (CMP, Ion,
Wafer $4B Photoresist, etc.) $5B
• Analog, Discrete $25B
Back-End Manufacturing $6B
• Bonding $1B
• Packaging $2B
Chips • Test equipment $3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

21/12/7 Dragon Star Shot Course 25

 Interconnect
Exploding number of metal layers, mask cost
Large number of vias diminishes yield
Increasingly complex process rules
 Via • Include pattern density
Stack & shape management i
Multiple n layout, extraction
Array
• Limit vias / multiple via
 Metal
s
Min, max, spacing, width
 Antenna
 Signal EM
Number of vias for a given load, frequency

21/12/7 Dragon Star Shot Course 26

 CD Variation Across a Wafer
Wafer Map for No-DPC Horizontal Isolated
Structures
LineWidth [nm]

x 10-7
2.3
2.2
2.1
2.0
1.9
1.8
150
100 60
50 40
20
Wafer Y 0 0 Wafer Y

Incorporate analysis of timing

variation into extraction &
static timing analysis

21/12/7
Source: Spanos, UCB Dragon Star Shot Course 27
 Physical design for Yield /
Reliability
Aggressive via minimization in routing

Insert redundant vias

Space / Width
Limit Current Density

21/12/7 Dragon Star Shot Course 28

 Back-End: Assembly and
Packaging Masks $2.8B
Systems EDA $3.6B
$1050B
Design Mask Data • Manufacturing $2.3B
• Computers • Tools $0.5B
• Communications EDA $2.7B
Masks
• Consumer Comp Platforms
• Industrial, Military…
Embedded SW $0.8B Front-End Manufacturing $24B
IP $0.9B • Process Auto $1B
• Lithography $6B
Semiconductors $119B • Etch/Doping $6B
• Micros, DSP $45B • Diffusion $1B
• Memory $25B • Deposition $5B
• ASIC, ASSP • Other (CMP, Ion,
$25B Wafer $4B Photoresist, etc.) $5B
• Analog, Discrete $25B
Back-End Manufacturing $6B
• Bonding $1B
• Packaging $2B
Chips • Test equipment $3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

21/12/7 Dragon Star Shot Course 29

 Assembly and Packaging
The chip is assembled into a package that
provides the contact leads for the chip. A wire-
bonding machine attaches wires to the leads of
the package; or this is achieved using flip chip
die attach.
Modern packages can be very complex
The package is the bridge between silicon and
system
Differentiator: Performance, form factor, fit,
thermal conduction, reliability, and cost

21/12/7 Dragon Star Shot Course 30

 IC / Package Co-Design for Flip
Lid Chip
Chip

Package
Pwr, Gnd
Signal
Solder
balls
Board
• Analyis • Design
• Extraction RLC • Package feasibility
• Simulation Spice • Bump patterning, assignment
• P/G assignment
• Driver placement
• Routing
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 SoC Packaging
Trends by 2005
 Cost: 0.29¢ to 2.28¢ / pin
 Pins / package: 120 – 3000
 Performance: 600 MHz – 2GHz
Integrating complete (sub)systems on a chip is often
driven by packaging
 Less I/O, power, area, & cost
 Higher on-chip speed, reliability
Complex packages and Multi-chip modules that
require routing and analysis, driven by mixed-signal,
RF, memory integration

21/12/7 Dragon Star Shot Course 32

 Back-End: Testing and
Automatic Test Equipment
Systems $1050B EDA $3.6B Masks $2.8B
Design Mask Data • Manufacturing $2.3B
• Computers • Tools $0.5B
• Communications EDA $2.7B
Masks
• Consumer Comp Platforms
• Industrial, Military…
Embedded SW $0.8B Front-End Manufacturing $24B
IP $0.9B • Process Auto $1B
• Lithography $6B
Semiconductors $119B • Etch/Doping $6B
• Micros, DSP $45B • Diffusion $1B
• Memory $25B • Deposition $5B
• ASIC, ASSP • Other (CMP, Ion,
$25B Wafer $4B Photoresist, etc.) $5B
• Analog, Discrete $25B
Back-End Manufacturing $6B
• Bonding $1B
• Packaging $2B
Chips • Test equipment $3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

21/12/7 Dragon Star Shot Course 33

 Key Trends
By 2005
 Cost: $2-5k/pin ( high performance)
 Pins / package: 1900
 Performance: up to 2 GHZ
Tester timing accuracy growing at 12% per year
ASIC speeds growing at 30% per year
IDDQ becoming less meaningful
 For every 80mV of VT decrease Ioff increases 10x!!
 Higher leakage currents make IDDQ values increase dramatically
as transistor density increases
More mixed-signal testing

21/12/7 Dragon Star Shot Course 34

 Agenda
Dealing with technology
 Masks
 Front-end manufacturing
 Back-end manufacturing
Application requirements
Putting it all together

21/12/7 Dragon Star Shot Course 35

 Application Requirements
Systems $1050B EDA $3.6B Masks $2.8B
Design Mask Data • Manufacturing $2.3B
• Computers • Tools $0.5B
• Communications EDA $2.7B
Masks
• Consumer Comp Platforms
• Industrial, Military…
Embedded SW $0.8B Front-End Manufacturing $24B
IP $0.9B • Process Auto $1B
• Lithography $6B
Semiconductors $119B • Etch/Doping $6B
• Micros, DSP $45B • Diffusion $1B
• Memory $25B • Deposition $5B
• ASIC, ASSP $25B • Other (CMP, Ion,
Wafer $4B Photoresist, etc.) $5B
• Analog, Discrete $25B
Back-End Manufacturing $6B
• Bonding $1B
• Packaging $2B
Chips • Test equipment $3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

21/12/7 Dragon Star Shot Course 36

 Heterogeneity - SoC
Digital Analog
 Control RF
 µP Power
 DSP
MEMs
 Interfaces
Memory IP
 SRAM
 DRAM
 FLASH

21/12/7 Dragon Star Shot Course 37

 What EDA Must Provide…
System level design
Soc design&test, verification
methodology
Need hierarchy in the design f
low
Analog, digital, RF, MEMs
IP for soc construction / verifi
cation: processors, memory,
peripherals, etc.
Soc design for debug (debug
busses and controllers)

21/12/7 Dragon Star Shot Course 38

ASIC, ASSP, ASIP, GA, FPGA
ASIC & ASSP differ only by how they are sold and used, not b
y how they are designed
Early market characteristics  ASICs
Late market characteristics  ASSPs
Trend toward application-specific instruction processors
 Many processors on a chip
Metal Programmability (GA) gaining attention again
SW Programmable (FPGA), reconfigurable parts gaining impor
tance
Embedded FPGA / GA

21/12/7 Dragon Star Shot Course 39

 Power
1400
Dynamic
1200
power
1000 density
800
mW/mm2

600

400 Leakage
power
200
density
0
0.18 µm 0.13 µm 0.10 µm 0.05 µm

21/12/7 Dragon Star Shot Course 40

Solutions for Low Power Design
Power modeling and analysis
Clock gating and clock tree optimization
Variable Vdd
 Power gating
 Multi - Vdd
 Dynamic voltage scaling
Leakage optimization using multi-Vt
Modelling process variation
Support Asynchronous design

21/12/7 Dragon Star Shot Course 41

 Dual Vt
180nm 130nm
Leakage Power Leakage Power
Vdd (V) Delay (ps) Min (nW) Aver (nW) Max(nW) Vdd (V) Delay (ps) Min (nW) Aver (nW) Max (nW)
Low Vt 1.8 28 0.011 0.263 0.955 Low Vt 1.2 10 1.135 30.779 233.395

Leakage power [0.0-240.0] nW

High Vt 1.8 36 0.007 0.068 0.280 High Vt 1.2 16 0.002 0.043 0.580
Leakage power [0.0-1.0] nW

Big/Small 1.286 1.571 3.868 3.411 Big/Small 1.600 567.500 715.791 402.405

Cell number [0-467] Cell number [0-519]

21/12/7 Dragon Star Shot Course 42

From Ali Dasdan
 Speed
Determined by interconnect
The primary physical effect of concern is cross-
coupled capacitance plus the Miller effect. This
may cause:
 functional errors in analog
circuitry or dynamic logic V
dd R
V = IR

 timing errors in static digital I V -V

dd

circuitry R

IR Drop (static leakage and dynamic IR drop) V

ss

handled in power
Other important effects & features are
Inductance, CD variation, EM

21/12/7 Dragon Star Shot Course 43

 Agenda
Dealing with technology
 Masks
 Front-end manufacturing
 Back-end manufacturing
Application requirements
Putting it all together

21/12/7 Dragon Star Shot Course 44

 Putting it All Together: EDA
Systems $1050B EDA $3.6B Masks $2.8B
Design Mask Data • Manufacturing $2.3B
• Computers • Tools $0.5B
• Communications EDA $2.7B
Masks
• Consumer Comp Platforms
• Industrial, Military…
Embedded SW $0.8B Front-End Manufacturing $24B
IP $0.9B • Process Auto $1B
• Lithography $6B
Semiconductors $119B • Etch/Doping $6B
• Micros, DSP $45B • Diffusion $1B
• Memory $25B • Deposition $5B
• ASIC, ASSP • Other (CMP, Ion,
$25B Wafer $4B Photoresist, etc.) $5B
• Analog, Discrete $25B
Back-End Manufacturing $6B
• Bonding $1B
• Packaging $2B
Chips • Test equipment $3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

21/12/7 Dragon Star Shot Course 45

 SoC Design
Design Services

Synthesis
Physical

Power
Architecture Design

Test

Assertions and Testbenches

Timing and Signal Integrity

IP

Design Database
Design Planning

Verification IP

Languages
Physical Implementation Smart Verification

Extraction

Physical Verification
Mixed Signal / Analog
Mask Synthesis / OPC

21/12/7 Dragon Star Shot Course 46

 Implementation Nodes
180nm 130nm 90nm 65nm
Computing Parallelism
64 Bits
IP IP 30% 50% 70% 90%
Flow Hierarchy Large designs
Database Partial Partial Integrated Integrated
API Proprietary Open Open Open
S, P&R S, P&R S&P - R S&P - R Integrated Integrated
Handoff Placed Gates Placed Gates Layout Layout
Timing TC
SI
L for Busses 1.5GHz 1.5GHz 1.5GHz
Clocking Cycles across Chip 1 Few Few Many
Clocking Sync Sync Sync/Async Sync/Async
IR drop Power Power Power Power&Signal

21/12/7 Dragon Star Shot Course 47

 Implementation Nodes
180nm 130nm 90nm 65nm
Power Clock Gating
Multi Vdd
Multi Vth (leakage)
Test Scan
Mem Bist
Logic Bist
Design for Debug
RET OPC
PSM
DR for RET
DFM Statistical Timing
PD for DFM
Analog P&R Manual Semi-Auto Semi-Auto Semi-Auto
Synthesis Manual Manual Semi-Auto Semi-Auto
Package Spice Chip/Pack.
P&R Chip/Pack.

21/12/7 Dragon Star Shot Course 48

 Functional Verification
Driven by complexity
Verification models (IP)
Architecture
Design Avenues of development

Assertions and Testbenches

 Higher levels
 Performance
Verification IP

 Integration
Languages  New (formal) technologies
Smart Emulation competes with
Verification  Prototyping (enabled by multi-million
gate FPGAs)
 Compute farms (Linux)

Mixed Signal /
Analog

21/12/7 Dragon Star Shot Course 49

 Functional Verification 2003
Standard based IP, Star IP on AMBA
(System) Verilog for HW
Architecture SystemC for system level design (SW)
Design Languages for testbenches, assertions being stan

Assertions and Testbenches

dardized
Integrated simulation
(System)Verilog/VHDL
Verification IP

Languages  Fast Spice/Spice

Smart Testbenches
Verification
 Language
 Assertions (monitor)
 Constraint solver
Formal verification
 Equivalence checking
 Semi-Formal property checking
Mixed Signal /
Analog

21/12/7 Dragon Star Shot Course 50

 Summary
Dealing with technology
 Masks
RET, OPC, PSM
 Front-end manufacturing
Interconnect, CD variation, dishing, DFM
 Back-end manufacturing
Packaging, test
Application requirements
 Heterogeneity, cost, power, speed
Putting it all together
 Implementation flow, verification flow

21/12/7 Dragon Star Shot Course 51