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11unit 3 Data Path Implementation

The document discusses the stages of a datapath implementation. It breaks down the process of executing an instruction into 5 stages: 1) Instruction Fetch, 2) Instruction Decode, 3) ALU, 4) Memory Access, and 5) Register Write. This allows the datapath to be designed as smaller, more efficient stages that can be optimized independently. Common instructions are then walked through as examples of how they progress through each stage.

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118 views

11unit 3 Data Path Implementation

The document discusses the stages of a datapath implementation. It breaks down the process of executing an instruction into 5 stages: 1) Instruction Fetch, 2) Instruction Decode, 3) ALU, 4) Memory Access, and 5) Register Write. This allows the datapath to be designed as smaller, more efficient stages that can be optimized independently. Common instructions are then walked through as examples of how they progress through each stage.

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sn
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© © All Rights Reserved
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Download as PPTX, PDF, TXT or read online on Scribd
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Data Path Implementation

Stages of a Datapath
• Problem: a single, atomic block which “executes an
instruction” (performs all necessary operations
beginning with fetching the instruction) would be too
bulky and inefficient.
• Solution: break up the process of “executing an
instruction” into stages, and then connect the stages
to create the whole datapath
– Smaller stages are easier to design.
– Easy to optimize (change) one stage without touching the
others.
Stages of a Datapath (2)
• There is a wide variety of MIPS instructions:
so what general steps do they have in common?
• Stages
1. Instruction Fetch
2. Instruction Decode
3. ALU
4. Memory Access
5. Register Write
Stages of a Datapath (3)
• Stage 1: Instruction Fetch.
• No matter what the instruction is, the 32-bit
instruction word must first be fetched from
memory (the cache-memory hierarchy).

• Also, this is where we increment PC (that is,


PC = PC + 4, to point to the next instruction;
byte addressing so + 4).
Stages of a Datapath (4)
• Stage 2: Instruction Decode
• Upon fetching the instruction, we next gather data
from the fields (decode all necessary instruction
data).
• First, read the opcode to determine instruction type
and field lengths.
• Second, read in data from all necessary registers.
– For add, read two registers.
– For addi, read one register.
– For nop, no read necessary.
Stages of a Datapath (5)
• Stage 3: ALU (Arithmetic-Logic Unit)
• The real work of most instructions is done here:
arithmetic (+, -, *, /), shifting, logic (&, |),
comparisons .
• What about loads and stores?
– lw $t0, 40($t1)
– The address we are accessing in memory = the
value in $t1 plus the value 40.
– We do this addition at this stage.
Stages of a Datapath (6)
• Stage 4: Memory Access
• Actually only the load and store instructions do
anything during this stage; for the other
instructions, they remain idle during this stage.
• Since these instructions have a unique step, we
need this extra stage to account for them.
• As a result of the cache system, this stage is
expected to be just as fast (on average) as the
others
Stages of a Datapath (7)
• Stage 5: Register Write
• Most instructions write the result of some
computation into a register.
• Examples: arithmetic, logical, shifts, loads.
• What about stores, branches, jumps?
– They do not write anything into a register at the
end.
– These remain idle during this fifth stage.
Datapath: Generic Steps
Datapath Walkthroughs: add
• add $r3, $r1, $r2 # r3 = r1+r2
• Stage 1: Fetch this instruction, increment PC.
• Stage 2: Decode to find that it is an add
instruction, then read registers $r1 and $r2.
• Stage 3: Add the two values retrieved in stage 2.
• Stage 4: Idle (nothing to write to memory).
• Stage 5: Write result of stage 3 into register $r3.
Datapath Walkthroughs: add (2)
MACHINE INSTRUCTION CHARACTERISTICS

• The operation of the processor is determined


by the instructions it executes, referred to as
machine instructions or computer instructions.
• The collection of different instructions that
the processor can execute is referred to as the
processor’s instruction set.
Instruction Cycle State Diagram
Elements of a Machine Instruction
• Elements of a Machine Instruction
– Operation code
– Source operand reference
– Result operand reference
– Next instruction reference
• Source and result operands can be in one of four areas:
– Main or virtual memory:
– Processor register
– Immediate
– I/O device
Instruction Representation
• A Simple Instruction Format

• Opcode example
• ADD,SUB MUL,DIV,LOAD, STORE
Instruction Type
• Data processing:
– Arithmetic and logic instructions
• Data storage:
– Movement of data into or out of register and or
memory locations
• Data movement:
– I/O instructions
• Control:
– Test and branch instructions
Number of Addresses
• Three Address Instruction
• Instruction Comment
– SUB Y, A, B Y A - B
– MPY T, D, E TDxE
– ADD T, T, C TT+ C
– DIV Y, Y, T Y Y / T
Number of Addresses
• Two-address instructions
• Instruction Comment
• MOVE Y, A Y  A
• SUB Y, B Y  Y-B
• MOVE T, D T D
• MPY T, E T TxE
• ADD T, C T T+C
• DIV Y, T YY/T
Number of Addresses
• One-address instructions
• Instruction Comment
• LOAD D AC  D
• MPY E AC AC x E
• ADD C AC  AC + C
• STOR Y Y AC
• LOAD A AC  A
• SUB B AC  AC - B
• DIV Y AC  AC / Y
Utilization of Instruction Addresses
(Nonbranching Instructions)

Number of Addresses Symbolic Representation Interpretation


3 OP A, B, C A  B OP C
2 OP A, B A  A OP B
1 OP A AC  AC OP A
0 OP T  (T - 1) OP T

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