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Reduction of Leakage Current in 6t SRAM Cell

This document presents a project that aims to reduce leakage current in 6T SRAM cells using a MTCMOS technique. It first describes the basic structure and operation of a conventional 6T SRAM cell. It then introduces the MTCMOS technique, which uses high threshold voltage transistors at the supply rails to minimize leakage when the cell is not active. Simulation results show that the proposed MTCMOS SRAM cell achieves a reduction in leakage current compared to a conventional 6T SRAM cell. The document concludes that this structure is effective at reducing leakage current in SRAM cells.

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Praveen Saxena
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97 views16 pages

Reduction of Leakage Current in 6t SRAM Cell

This document presents a project that aims to reduce leakage current in 6T SRAM cells using a MTCMOS technique. It first describes the basic structure and operation of a conventional 6T SRAM cell. It then introduces the MTCMOS technique, which uses high threshold voltage transistors at the supply rails to minimize leakage when the cell is not active. Simulation results show that the proposed MTCMOS SRAM cell achieves a reduction in leakage current compared to a conventional 6T SRAM cell. The document concludes that this structure is effective at reducing leakage current in SRAM cells.

Uploaded by

Praveen Saxena
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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PBL PRESENTATION ON REDUCTION

OF LEAKAGE CURRENT IN SRAM


SUBMITTED TO-- SUBMITTED
BY--
Contents
• Abstract
• Introduction
• 6T SRAM Cell
• Working of 6T SRAM in READ, WRITE and HOLD
state
-Simulation Result
• Leakage Reduction – MTCMOS Technique
-Simulation Result
• Conclusion
• Acknowledgement
• References
Abstract
• The aim of this paper is to reduce the leakage
current of 6T SRAM using MTCMOS technique.
• This work introduces a technique based on
high threshold NMOS and PMOS transistors
working together to minimise the leakage
current of 6T SRAM.
• In this paper, we propose a structure of SRAM
using NMOS and PMOS at ground and Vdd
supply to reduce leakage.
Introduction
• SRAM is a static memory. Static random-access
memory is a type of semiconductor memory that
uses bistable latching circuitry (flip-flop)to store each
bit.
• The term “static” is derived from the fact that it
doesn’t need to be refreshed like dynamic RAM.
• Has cycle time much shorter than that of DRAM
because it does not need to pause between
accesses.
Introduction cont.
• Data stored as long as supply is applied.
• It is large i.e. 6 transistors per cell.
• It is fast.
• It is more reliable as periodic refreshing not
required.
• It often only used as a memory cache.
Conventional 6T SRAM Cell
M1, M2, M3, M4 –
MEMORY
M5, M6 –
ACCESS TRANSISTOR

WL – WORD LINE
-WL=1 for READ AND
WRITE
-WL=0 for HOLD

BL &BLB – BIT LINE


-ACT as i/p for WRITE
-ACT as o/p for READ

PRECHARGE CAPACITORS
-In READ & WRITE operat..
Q & QB -- OUTPUTS
OF INVERTER.
READ OPERATION -- Q=1 & QB =0
-- WL = 1
-- BL & BLB = OUTPUT

-- AT BL=Vdd & Q=1,


NO VOLTAGE DIFFERENCE SO
CAPACITOR WILL NOT
DISCHARGE
--AT BLB=1 & QB=0,
THERE IS DIFFERENCE SO BLB
VOLTAGE WILL DECREASE
--BL & BLB VALUES SENT
TO SENSE AMPLIFIER
WHICH WILL ACT AS
COMPARATOR
-IF BLB DECREASE THEN,
O/P =1
WRITE OPERATION -- Q=0 & QB =1

-- WL = 1

-- BL & BLB = INPUT

-- BLB = GROUND

-- VOLTAGE DECREASES DUE


TO GROUND

-- If V is less than Vth of


N1, then N1 will be OFF
& P1 will be ON

-- P1= ON means Q will get


value of Vdd i.e
OUTPUT=1(Q)
Simulation Results

*leakage current value for normal operation of SRAM is “1.9741E-08”


Leakage Reduction – MTCMOS Technique
Multi-threshold CMOS --
(MTCMOS) is a variation of CMOS
chip technology which has
transistors with multiple threshold
voltages (Vth) in order to optimize
delay or power.

--We will apply high Vdd at PMOS


Transistor which turn it in sleep
mode ie. OFF.

--Similarly We will apply 0 on NMOS


Transistor, thus it reduces sub-
threshold leakage during sleep
mode.
MTCMOS Technique cont.
• In a "fine-grained" approach, high Vth sleep
transistors are incorporated within every gate.
Low Vth transistors are used for the pull-up
and pull-down networks, and a high Vth
transistor is used to gate the leakage current
between the two networks.
• This approach eliminates problems of logic
block partitioning and sleep transistor sizing.
Simulation Result
Conclusion
• In this paper, we propose a structure of SRAM
using two high threshold transistors.
• In proposed MTCMOS based 6T SRAM cell, the
total leakage current %

Conventional SRAM Proposed MTCMOS


Cell SRAM Cell

Leakage Current
Acknowledgement

• This work was supported by ITM Universe,


Gwalior. The authors would also like to thank
to Professor Dr. Saurabh Khandelwal Sir for
their enlightening technical advice.
References
• https://en.wikipedia.org/wiki/Static_random-
access_memory
• Anis, M.; Areibi; Mahmoud; Elmasry (2002).
"Dynamic and leakage power reduction in
MTCMOS circuits". Design Automation
Conference, 2002. Proceedings. 39th: 480–485.
ISBN 1-58113-461-4.
• Oklobdzija, Vojin G. (1997). Digital Design and
Fabrication. CRC-Press. pp. 12–18. ISBN 978-0-
8493-8602-2.
• https://en.wikipedia.org/wiki/Multi-
threshold_CMOS
Thank You

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