ELEC 7770

Advanced VLSI Design

Spring 2007
VLSI System DFT
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07
Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 1
 SOC Design: A DFT Problem

 Given the changing scenario in VLSI:

 Mixed-signal circuits
 System-on-a-chip
 Multi-chip modules
 Intellectual property (IP) cores
 A system must be designed for testability.

Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 2

 Conventional Test:
In-Circuit Test (ICT)
 A bed-of-nails fixture provides direct access to each
chip on the board.
 Advantages: Thorough test for devices; good
interconnect test.
 Limitations:
 Works best when analog and digital functions are
implemented on separate chips.
 Devices must be designed for backdriving protection.
 Not applicable to system-on-a-chip (SOC).
 Disadvantages:
 High cost and inflexibility of test fixture.
 System test must check for timing.
Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 3
 PCB vs. SOC

PCB SOC

 Tested parts  High reliability

 In-circuit test (ICT)  Fast interconnects
 Easy test access  Low cost
 Bulky  Untested cores
 Slow  No internal test
 High assembly cost access
 Mixed-signal devices

Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 4

 SOC: Core-Based Design
 Cores are predesigned and verified but
untested blocks:
 Soft core (synthesizable RTL)
 Firm core (gate-level netlist)
 Hard core (non-modifiable layout, often called
legacy core)
 Core is the intellectual property of vendor
(internal details not available to user.)
 Core-vendor supplied tests must be applied
to embedded cores.
Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 5
 Partitioning for Test
 Partition according to test methodology:
 Logic blocks
 Memory blocks
 Analog blocks
 Provide test access:
 Boundary scan
 Analog test bus
 Provide test-wrappers (also called collars)
for cores.

Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 6

 Test-Wrapper for a Core
 Test-wrapper (or collar) is the logic added around a
core to provide test access to the embedded core.
 Test-wrapper provides:
 For each core input terminal
 A normal mode – Core terminal driven by host chip
 An external test mode – Wrapper element observes core
input terminal for interconnect test
 An internal test mode – Wrapper element controls state of
core input terminal for testing the logic inside core
 For each core output terminal
 A normal mode – Host chip driven by core terminal
 An external test mode – Host chip is driven by wrapper
element for interconnect test
 An internal test mode – Wrapper element observes core
outputs for core test
Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 7
 A Test-Wrapper
Wrapper
elements

core outputs
core inputs
Functional

Functional
Scan chain
Scan chain Core

from/to
External
Test pins Scan chain Wrapper
test
controller
to/from TAP
Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 8
 References
 Test Wrapper:
 B. Nadeau-Dosti, Design for At-Speed Test, Diagnosis
and Measurement, Springer, 2000.
 System Test:
 R. Rajsuman, System-on-a-Chip: Design and Test,
Artech-House, 2000.
 M. L. Bushnell and V. D. Agrawal, Essentials of
Electronic Testing for Digital, Memory & Mixed-Signal
VLSI Circuits, Springer, 2000.

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 Overhead of Test Access
 Test access is non-intrusive.
 Hardware is added to each I/O signal of block
to be tested.
 Test access interconnects are mostly local.
 Hardware overhead is proportional to:
– 1/2
(Block area)

Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 10

 Overhead Estimate
Rent’s rule: For a logic block the number of gates G
and the number of terminals t are related by
a
t =KG

where 1 ≤ K ≤ 5, and a ~ 0.5.

Assume that block area A is proportional to G, i.e.,

t is proportional to A 0.5. Since test logic is added
to each terminal t,

Test logic added to terminals

–0.5
Overhead = ──────────────────── ~ A
A

Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 11

 DFT Architecture for SOC
Test Test
User defined test access mechanism (TAM)
source sink
Func.
outputs Functional
Functional Func. outputs
inputs

wrapper
inputs

wrapper
Module Module
Test

Test
1 N

Instruction register control

Test access port (TAP)

Serial instruction data
TRST
TDI

TMS
TCK

TDO
SOC inputs SOC outputs

Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 12

 DFT Components
 Test source: Provides test vectors via on-chip LFSR,
counter, ROM, or off-chip ATE.
 Test sink: Provides output verification using on-chip
signature analyzer, or off-chip ATE.
 Test access mechanism (TAM): User-defined test data
communication structure; carries test signals from
source to module, and module to sink; tests module
interconnects via test-wrappers; TAM may contain bus,
boundary-scan and analog test bus components.
 Test controller: Boundary-scan test access port (TAP);
receives control signals from outside; serially loads
test instructions in test-wrappers.
Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 13
 Related Topics
 IEEE 1500 standard
 Core Test Language (CTL):
 Test configuration(s)
 Test interfaces
 Test data (stimuli and responses)
 Reference
 Y. Zorian and A. Yessayan, “IEEE 1500 Utilization in
SOC Design and Test,” Proc. International Test Conf.,
November 2005.
 E. J. Marinissen, R. Kapur, M. Lousberg, T. McLaurin, M.
Ricchetti, and Y. Zorian, “On IEEE P1500 Standard for
Embedded Core Test,” J. Electronic Testing: Theory and
Applications, vol. 18, no. 4-5, pp. 365-383, August 2002.
Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 14
 Summary
 Functional test: verify system hardware, software, function and
performance; pass/fail test with limited diagnosis; high ( ~100%)
software coverage metrics; low ( ~70%) structural fault coverage.
 Diagnostic test: High structural coverage; high diagnostic
resolution; procedures use fault dictionary or diagnostic tree.
 SOC design for testability:
 Partition SOC into blocks of logic, memory and analog
circuitry, often on architectural boundaries.
 Provide external or built-in tests for blocks.
 Provide test access via boundary scan and/or analog test
bus.
 Develop interconnect tests and system functional tests.
 Develop diagnostic procedures.
 Test scheduling to minimize test time and test power.

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