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Hardware Description Language: - Tool For Specifying Hardware Circuits Types of HDL: - VHDL - Verilog

- Hardware Description Language (HDL) is a tool for specifying hardware circuits. The two main types of HDL are VHDL and Verilog. - Verilog uses keywords like module, input, output, and endmodule to define basic building blocks and connect ports. Primitive gates and registers can be instantiated. - Examples shown include a 2-to-4 line decoder, 4-to-1 multiplexer, 1-bit full adder, and 4-bit ripple carry adder defined using Verilog modules with input, output, and internal net declarations.

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33 views

Hardware Description Language: - Tool For Specifying Hardware Circuits Types of HDL: - VHDL - Verilog

- Hardware Description Language (HDL) is a tool for specifying hardware circuits. The two main types of HDL are VHDL and Verilog. - Verilog uses keywords like module, input, output, and endmodule to define basic building blocks and connect ports. Primitive gates and registers can be instantiated. - Examples shown include a 2-to-4 line decoder, 4-to-1 multiplexer, 1-bit full adder, and 4-bit ripple carry adder defined using Verilog modules with input, output, and internal net declarations.

Uploaded by

اسامه صلاح الدين
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Hardware Description language

• Tool for specifying hardware circuits

Types of HDL:
• VHDL
• Verilog
Levels of description
• Switch level
• Gate level
• Data flow level
• Behavioral level
Verilog Keywords & Constructs
• Keywords are lower case
• module – fundamental building block for Verilog
designs
– Used to construct design hierarchy
– Cannot be nested
• endmodule – ends a module – not a statement
=> no “;”
• Module Declaration
– module module_name (module_port, module_port, …);
– Example: module full_adder (A, B, c_in,
c_out, S);
Verilog Keywords & Constructs
• Input Declaration
– Scalar
• input list of input identifiers;
• Example: input A, B, c_in;
– Vector
• input[range] list of input identifiers;
• Example: input[15:0] A, B, data;
• Output Declaration
– Scalar Example: output c_out, OV, MINUS;
– Vector Example: output[7:0] ACC, REG_IN, data_out;
Basic structure of a Verilog module
Module module_name(list of ports);
input/output port declarations
Local net declarations
Parallel statements
endmodule
Verilog Keywords & Constructs
• Primitive Gates
– buf, not, and, or, nand, nor, xor, xnor
– Syntax: gate_operator instance_identifier (output,
input_1, input_2, …)
– Examples:
and A1 (F, A, B); //F = A B
or O1 (w, a, b, c)
O2 (x, b, c, d, e); //w=a+b+c,x=b+c+d+e
Nets
• Nets represent physical connections between hardware
elements
• Declared with the keyword wire
• Used to connect instantiated modules
• Must be continuously driven with a value
• Ex. wire b, c;
– Do not hold their value
– Take their value from a driver such as a gate or
other module
– Cannot be assigned in an initial or always block
Registers
• Registers represent storage elements

• Registers do not need to be continuously driven


• Registers will hold a value until another value is placed onto them

• Ex.
• reg reset;
• initial
• begin
• reset = 1’b1;
• #100 reset = 1’b0;
• end
Port connection rules
2-to-4 Line Decoder
2-to-4 Line Decoder
// 2-to-4 Line Decoder: Structural Verilog Desc.

module decoder_2_to_4_st_v(EN, A0, A1, D0, D1, D2, D3);


input EN, A0, A1;
output D0, D1, D2, D3;
wire A0_n, A1_n, N0, N1, N2, N3;
not
go(A0_n, A0),
g1(A1_n, A1);
and
g3(N0, A0_n, A1_n),
g4(N1, A0, A1_n),
g5(N2, A0_n, A1),
g6(N3, A0, A1),
g7(D0, N0, EN),
g8(D1, N1, EN),
g9(D2, N2, EN),
g10(D3, N3, EN);
endmodule
4-to-1 Line Multiplexer
4-to-1 Line Multiplexer
// 4-to-1-Line Multiplexer: Structural Verilog Description
// (See Figure 3-26 for logic diagram)
module multiplexer_4_to_1_st_v(S, I, Y);
input [1:0] S;
input [3:0] I;
output Y;

wire [1:0] not_S;


wire [0:3] D, N;

not
gn0(not_S[0], S[0]),
gn1(not_S[1], S[1]);

and
g0(D[0], not_S[1], not_S[0]),
g1(D[1], not_S[1], S[0]),
g2(D[2], S[1], not_S[0]),
g3(D[3], S[1], S[0]);
g0(N[0], D[0], I[0]),
g1(N[1], D[1], I[1]),
g2(N[2], D[2], I[2]),
g3(N[3], D[3], I[3]);

or go(Y, N[0], N[1], N[2], N[3]);

endmodule
1 bit Full Adder
1-bit Full Adder
// define a 1-bit full adder
Module fulladd (sum, c_out, a, b, c_in);
// I/O port declarations
Output sum, c_out;
Input a, b, c_in;
//internal nets
Wire s1, c1, c2;
// instantiate logic gate primitives
Xor (s1, a, b);
And (c1, a, b);
Xor (sum, s1, c_in);
And (c2, s1, c_in);
Xor (c_out, c2, c1);
endmodule
4-bit Ripple Carry Adder
4-bit Full Adder
// define a 4-bit full adder
Module fulladd4 (sum, c_out, a, b, c_in);
// I/O port declarations
Output [3:0] sum;
Output c_out;
Input [3:0] a, b;
Input c_in;
// internal nets
Wire c1, c2, c3;
// instantiate four 1-bit full adders
Fulladd fa0(sum[0], c1, a[0], b[0], c_in);
Fulladd fa1(sum[1], c2, a[1], b[1], c1);
Fulladd fa2(sum[2], c3, a[2], b[2], c2);
Fulladd fa3(sum[3], c_out, a[3], b[3], c3);
endmodule

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