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I F P G A (Fpga) : Ntroduction To Ield Rogrammable ATE Rrays S

Field programmable gate arrays (FPGAs) can be reconfigured to implement any digital logic function. More recent FPGA architectures include block RAM arrays, multiplier cores, and processor cores. The basic FPGA architecture consists of configurable logic blocks (CLBs) containing lookup tables and flip flops, programmable interconnects, and input/output blocks. FPGAs can be configured through serial or parallel interfaces and support partial reconfiguration during operation.

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77 views13 pages

I F P G A (Fpga) : Ntroduction To Ield Rogrammable ATE Rrays S

Field programmable gate arrays (FPGAs) can be reconfigured to implement any digital logic function. More recent FPGA architectures include block RAM arrays, multiplier cores, and processor cores. The basic FPGA architecture consists of configurable logic blocks (CLBs) containing lookup tables and flip flops, programmable interconnects, and input/output blocks. FPGAs can be configured through serial or parallel interfaces and support partial reconfiguration during operation.

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vidhya ds
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INTRODUCTION TO FIELD

PROGRAMMABLE GATE ARRAYS


(FPGAS)
FIELD PROGRAMMABLE ARRAYS
 Dominant digital design implementation
 Ability to re-configure FPGA to implement any
digital logic function
 Partial re-configuration allows a portion of the FPGA
to be continuously running while another portion is
being re-configured
 FPGAs also contain analog circuitry features
including a programmable slew rate and drive
strength, differential comparators on I/O
designed to be connected to differential signaling
channels.
 Mixed-signal FPGAs contains ADCs and DACs
with analog signal conditional blocks allowing
them to operate as a system-on-chip (SoC)
FPGA ARCHITECTURES
 Early FPGAs
 N x N array of unit cells (CLB + routing)
 Special routing along center axis
 Next Generation FPGAs
 M x N unit cells
 Small block RAMs around edges

 More recent FPGAs


 Added block RAM arrays
 Added multiplier cores
 Adders processor cores
FPGA ARCHITECTURE TRENDS
 Memories
 Single & Dual-port RAMS
 FIFO (first-in first-out)
 ECC (error correcting codes)
 Digital Signal Processors
 Multipliers
 Accumulators
 Arithmetic Logic Units (ALUs)
 Embedded Processors
 Hardcore (dedicated processors)
 Dedicated program and data memories
 Programmable RAM in FPGA can be used in conjunction with
the processor to provide program and data memories
 Soft core (synthesized from a HDL)
BASIC FPGA ARCHITECTURE

•More recent FPGA architectures have small block RAM arrays (usually
placed in center column), multipliers, processor cores, DSP cores w/
multipliers, and I/O cells along columns for BGAs.
FPGA OPERATION
User writes configuration memory
which defines the function of the
system. This includes: the connectivity
between the CLBs and the I/O cells, the
logic to be implemented onto the CLBs,
and the I/O blocks.

By changing the data in the


configuration memory, the function of
the system changes as well. This change
in data can be implemented at anytime
during FPGA operation (run-time
configuration).
CONFIGURABLE LOGIC BLOCKS (CLBS)
ARCHITECTURE
 CLBs consist of:
 Look-up Tables (LUT) which implement the entries of a logic
functions truth table
 Some FPGAs can use LUTs to implement small Random Access
Memory (RAM)
 Carry and Control Logic
 Implements fast arithmetic operations (adders/ subtractors)
 Can be also configured for additional operations (Built-in-Self Test
iterative-OR chain)
 Memory Elements
 Configurable Flip Flops (FFs)/ Latches( Programmable clock edges,
set/reset, and clock enable)
 These memory elements usually can be configured as shift-
registers
CONFIGURABLE LOGIC BLOCKS

A CLB can contain


several slices, which
make up a single CLB.
Xilinx Virtex-5 FPGAs
(right) have two slices:
SLICEL (logic) and
SLICEM (memory).

In addition to the basic


CLB architecture, the
Virtex-5 contains wide-
function MUXs which can
implement:
- 4:1 MUX using 1 LUT
- 8:1 MUX using 2 LUTs
- 16:1 MUX using 4 LUTs
LOOK-UP TABLES (2:1 MUX EXAMPLE)
 Configuration memory holds output of truth table
entries
 Internal signals connect to control signals of
MUXs to select a values of the truth tables for
any given input signals
FPGA PROGRAMMABLE
INTERCONNECTION NETWORK
 Horizontal and vertical mesh of wire segments interconnected by
programmable switches called programmable interconnect points (PIPs).
These PIPs are implemented using a transmission gate controlled by a
memory bits from the configuration memory.
 Consists of global routing connecting PLBs to I/O buffers, non-adjacent
PLBs, and other embedded components. Local routing connects PLBs to
other adjacent PLBs and PLBs to global routing (done through a switch
matrix)

 Several types of PIPs are used


 Cross-point = connects vertical or horizontal wire segments allowing turns
 Breakpoint = connects or isolates 2 wire segments
 Decoded MUX = group of 2^n cross-points connected to a single output configure by n configuration
bits
 Non-decoded MUX = n wire segments each with a configuration bit (n segments)
 Compound cross-point = 6 Break-point PIPS (can isolate two isolated signal nets)
PROGAMMABLE INPUT/OUTPUT CELLS
 Bi-directional Buffers
 Programmable for inputs or outputs
 Tri-state controls bi-directional operation
 Pull-up/down resistors
 FFs/ Latches are used to improve timing issues
 Set-up and hold times
 Clock-to-out delay

 Routing Resources
 Connections to core of array
 Programmable I/O voltage and current levels
Boundary Scan Access
FPGA CONFIGURATION INTERFACES
 Master (Serial or Parallel)
 FPGA retrieves configuration from ROM at initial
power-up
 Slave (Serial or Parallel)
 FPGA configured by an external source (i.e
microprocessor/ other FPGA)
 Used for dynamic partial re-configuration

 Boundary Scan
 4-wire IEEE standard serial interface used for
testing
 Write and read access to configuration memory
 Interfaces to FPGA core internal routing network
BOUNDARY SCAN CONFIGURATION
Multi-FPGA Emulation Framework
to support NoC design and
verification (UNLV NSIL)

Developed to test
interconnect between
chips on PCB

Daisy Chain
Test Access Point Configuration
(TAP) controller
composed of 16
state FSM

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